Intel 253666-024US Manuel D’Utilisation
Vol. 2A 2-3
INSTRUCTION FORMAT
opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpre-
dictable behavior.
The operand-size override prefix allows a program to switch between 16- and 32-bit
operand sizes. Either size can be the default; use of the prefix selects the non-default
size. Use of 66H followed by 0FH is treated as a mandatory prefix by some
SSE/SSE2/SSE3 instructions. Other use of the 66H prefix with MMX/SSE/SSE2/SSE3
instructions is reserved; such use may cause unpredictable behavior.
The address-size override prefix (67H) allows programs to switch between 16- and
32-bit addressing. Either size can be the default; the prefix selects the non-default
size. Using this prefix and/or other undefined opcodes when operands for the instruc-
tion do not reside in memory is reserved; such use may cause unpredictable
behavior.
dictable behavior.
The operand-size override prefix allows a program to switch between 16- and 32-bit
operand sizes. Either size can be the default; use of the prefix selects the non-default
size. Use of 66H followed by 0FH is treated as a mandatory prefix by some
SSE/SSE2/SSE3 instructions. Other use of the 66H prefix with MMX/SSE/SSE2/SSE3
instructions is reserved; such use may cause unpredictable behavior.
The address-size override prefix (67H) allows programs to switch between 16- and
32-bit addressing. Either size can be the default; the prefix selects the non-default
size. Using this prefix and/or other undefined opcodes when operands for the instruc-
tion do not reside in memory is reserved; such use may cause unpredictable
behavior.
2.1.2 Opcodes
A primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field is
sometimes encoded in the ModR/M byte. Smaller fields can be defined within the
primary opcode. Such fields define the direction of operation, size of displacements,
register encoding, condition codes, or sign extension. Encoding fields used by an
opcode vary depending on the class of operation.
Two-byte opcode formats for general-purpose and SIMD instructions consist of:
sometimes encoded in the ModR/M byte. Smaller fields can be defined within the
primary opcode. Such fields define the direction of operation, size of displacements,
register encoding, condition codes, or sign extension. Encoding fields used by an
opcode vary depending on the class of operation.
Two-byte opcode formats for general-purpose and SIMD instructions consist of:
•
An escape opcode byte 0FH as the primary opcode and a second opcode byte, or
•
A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, and a second
opcode byte (same as previous bullet)
opcode byte (same as previous bullet)
For example, CVTDQ2PD consists of the following sequence: F3 0F E6. The first byte
is a mandatory prefix for SSE/SSE2/SSE3 instructions (it is not considered as a
repeat prefix).
Three-byte opcode formats for general-purpose and SIMD instructions consist of:
is a mandatory prefix for SSE/SSE2/SSE3 instructions (it is not considered as a
repeat prefix).
Three-byte opcode formats for general-purpose and SIMD instructions consist of:
•
An escape opcode byte 0FH as the primary opcode, plus two additional opcode
bytes, or
bytes, or
•
A mandatory prefix (66H), an escape opcode byte, plus two additional opcode
bytes (same as previous bullet)
bytes (same as previous bullet)
For example, PHADDW for XMM registers consists of the following sequence: 66 0F
38 01. The first byte is the mandatory prefix.
Valid opcode expressions are defined in Appendix A and Appendix B.
38 01. The first byte is the mandatory prefix.
Valid opcode expressions are defined in Appendix A and Appendix B.