Intel 253666-024US Manuel D’Utilisation
3-316 Vol. 2A
FDIV/FDIVP/FIDIV—Divide
INSTRUCTION SET REFERENCE, A-M
FDIV/FDIVP/FIDIV—Divide
Description
Divides the destination operand by the source operand and stores the result in the
destination location. The destination operand (dividend) is always in an FPU register;
the source operand (divisor) can be a register or a memory location. Source oper-
ands in memory can be in single-precision or double-precision floating-point format,
word or doubleword integer format.
The no-operand version of the instruction divides the contents of the ST(1) register
by the contents of the ST(0) register. The one-operand version divides the contents
of the ST(0) register by the contents of a memory location (either a floating-point or
an integer value). The two-operand version, divides the contents of the ST(0)
register by the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of popping the FPU register
stack after storing the result. To pop the register stack, the processor marks the
ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-
operand version of the floating-point divide instructions always results in the register
stack being popped. In some assemblers, the mnemonic for this instruction is FDIV
rather than FDIVP.
The FIDIV instructions convert an integer source operand to double extended-preci-
sion floating-point format before performing the division. When the source operand
is an integer 0, it is treated as a +0.
destination location. The destination operand (dividend) is always in an FPU register;
the source operand (divisor) can be a register or a memory location. Source oper-
ands in memory can be in single-precision or double-precision floating-point format,
word or doubleword integer format.
The no-operand version of the instruction divides the contents of the ST(1) register
by the contents of the ST(0) register. The one-operand version divides the contents
of the ST(0) register by the contents of a memory location (either a floating-point or
an integer value). The two-operand version, divides the contents of the ST(0)
register by the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of popping the FPU register
stack after storing the result. To pop the register stack, the processor marks the
ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-
operand version of the floating-point divide instructions always results in the register
stack being popped. In some assemblers, the mnemonic for this instruction is FDIV
rather than FDIVP.
The FIDIV instructions convert an integer source operand to double extended-preci-
sion floating-point format before performing the division. When the source operand
is an integer 0, it is treated as a +0.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D8 /6
FDIV m32fp
Valid
Valid
Divide ST(0) by m32fp and store
result in ST(0).
DC /6
FDIV m64fp
Valid
Valid
Divide ST(0) by m64fp and store
result in ST(0).
D8 F0+i
FDIV ST(0), ST(i)
Valid
Valid
Divide ST(0) by ST(i) and store result
in ST(0).
DC F8+i
FDIV ST(i), ST(0)
Valid
Valid
Divide ST(i) by ST(0) and store result
in ST(i).
DE F8+i
FDIVP ST(i), ST(0)
Valid
Valid
Divide ST(i) by ST(0), store result in
ST(i), and pop the register stack.
DE F9
FDIVP
Valid
Valid
Divide ST(1) by ST(0), store result in
ST(1), and pop the register stack.
DA /6
FIDIV m32int
Valid
Valid
Divide ST(0) by m32int and store
result in ST(0).
DE /6
FIDIV m16int
Valid
Valid
Divide ST(0) by m64int and store
result in ST(0).