Intel 253666-024US Manuel D’Utilisation
3-386 Vol. 2A
FST/FSTP—Store Floating Point Value
INSTRUCTION SET REFERENCE, A-M
FST/FSTP—Store Floating Point Value
Description
The FST instruction copies the value in the ST(0) register to the destination operand,
which can be a memory location or another register in the FPU register stack. When
storing the value in memory, the value is converted to single-precision or double-
precision floating-point format.
The FSTP instruction performs the same operation as the FST instruction and then
pops the register stack. To pop the register stack, the processor marks the ST(0)
register as empty and increments the stack pointer (TOP) by 1. The FSTP instruction
can also store values in memory in double extended-precision floating-point format.
If the destination operand is a memory location, the operand specifies the address
where the first byte of the destination value is to be stored. If the destination
operand is a register, the operand specifies a register in the register stack relative to
the top of the stack.
If the destination size is single-precision or double-precision, the significand of the
value being stored is rounded to the width of the destination (according to the
rounding mode specified by the RC field of the FPU control word), and the exponent
is converted to the width and bias of the destination format. If the value being stored
is too large for the destination format, a numeric overflow exception (#O) is gener-
ated and, if the exception is unmasked, no value is stored in the destination operand.
If the value being stored is a denormal value, the denormal exception (#D) is not
generated. This condition is simply signaled as a numeric underflow exception (#U)
condition.
If the value being stored is ±0, ±∞, or a NaN, the least-significant bits of the signifi-
which can be a memory location or another register in the FPU register stack. When
storing the value in memory, the value is converted to single-precision or double-
precision floating-point format.
The FSTP instruction performs the same operation as the FST instruction and then
pops the register stack. To pop the register stack, the processor marks the ST(0)
register as empty and increments the stack pointer (TOP) by 1. The FSTP instruction
can also store values in memory in double extended-precision floating-point format.
If the destination operand is a memory location, the operand specifies the address
where the first byte of the destination value is to be stored. If the destination
operand is a register, the operand specifies a register in the register stack relative to
the top of the stack.
If the destination size is single-precision or double-precision, the significand of the
value being stored is rounded to the width of the destination (according to the
rounding mode specified by the RC field of the FPU control word), and the exponent
is converted to the width and bias of the destination format. If the value being stored
is too large for the destination format, a numeric overflow exception (#O) is gener-
ated and, if the exception is unmasked, no value is stored in the destination operand.
If the value being stored is a denormal value, the denormal exception (#D) is not
generated. This condition is simply signaled as a numeric underflow exception (#U)
condition.
If the value being stored is ±0, ±∞, or a NaN, the least-significant bits of the signifi-
cand and the exponent are truncated to fit the destination format. This operation
preserves the value’s identity as a 0, ∞, or NaN.
preserves the value’s identity as a 0, ∞, or NaN.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
D9 /2
FST m32fp
Valid
Valid
Copy ST(0) to m32fp.
DD /2
FST m64fp
Valid
Valid
Copy ST(0) to m64fp.
DD D0+i
FST ST(i)
Valid
Valid
Copy ST(0) to ST(i).
D9 /3
FSTP m32fp Valid
Valid
Copy ST(0) to m32fp and pop register
stack.
DD /3
FSTP m64fp Valid
Valid
Copy ST(0) to m64fp and pop register
stack.
DB /7
FSTP m80fp Valid
Valid
Copy ST(0) to m80fp and pop register
stack.
DD D8+i
FSTP ST(i)
Valid
Valid
Copy ST(0) to ST(i) and pop register
stack.