Intel 253666-024US Manuel D’Utilisation
Vol. 2A 2-15
INSTRUCTION FORMAT
The ModR/M encoding for RIP-relative addressing does not depend on using prefix.
Specifically, the r/m bit field encoding of 101B (used to select RIP-relative
addressing) is not affected by the REX prefix. For example, selecting R13 (REX.B = 1,
r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/m
field of REX.B combined with ModR/M is not fully decoded. In order to address R13
with no displacement, software must encode R13 + 0 using a 1-byte displacement of
zero.
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The
use of the address-size prefix does not disable RIP-relative addressing. The effect of
the address-size prefix is to truncate and zero-extend the computed effective
address to 32 bits.
Specifically, the r/m bit field encoding of 101B (used to select RIP-relative
addressing) is not affected by the REX prefix. For example, selecting R13 (REX.B = 1,
r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/m
field of REX.B combined with ModR/M is not fully decoded. In order to address R13
with no displacement, software must encode R13 + 0 using a 1-byte displacement of
zero.
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The
use of the address-size prefix does not disable RIP-relative addressing. The effect of
the address-size prefix is to truncate and zero-extend the computed effective
address to 32 bits.
2.2.1.7
Default 64-Bit Operand Size
In 64-bit mode, two groups of instructions have a default operand size of 64 bits (do
not need a REX prefix for this operand size). These are:
not need a REX prefix for this operand size). These are:
•
Near branches
•
All instructions, except far branches, that implicitly reference the RSP
2.2.2
Additional Encodings for Control and Debug Registers
In 64-bit mode, more encodings for control and debug registers are available. The
REX.R bit is used to modify the ModR/M reg field when that field encodes a control or
debug register (see Table 2-4). These encodings enable the processor to address
CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit
mode. CR8 becomes the Task Priority Register (TPR).
In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not imple-
mented. Any attempt to access unimplemented registers results in an invalid-opcode
exception (#UD).
REX.R bit is used to modify the ModR/M reg field when that field encodes a control or
debug register (see Table 2-4). These encodings enable the processor to address
CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit
mode. CR8 becomes the Task Priority Register (TPR).
In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not imple-
mented. Any attempt to access unimplemented registers results in an invalid-opcode
exception (#UD).
Table 2-7. RIP-Relative Addressing
ModR/M and SIB Sub-field
Encodings
Compatibility
Mode Operation
64-bit Mode
Operation
Additional Implications
in 64-bit mode
ModR/M
Byte
mod == 00
Disp32
RIP + Disp32
Must use SIB form with
normal (zero-based)
displacement addressing
r/m == 101 (none)
SIB Byte
base == 101 (none) if mod = 00,
Disp32
Same as
legacy
None
index == 100
(none)
scale = 0, 1, 2, 4
scale = 0, 1, 2, 4