Intel 253666-024US Manuel D’Utilisation
Vol. 2A 3-415
INSTRUCTION SET REFERENCE, A-M
FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State
FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR State
Description
Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte
memory image specified in the source operand. This data should have been written
to memory previously using the FXSAVE instruction, and in the same format as
required by the operating modes. The first byte of the data should be located on a
16-byte boundary. There are three distinct layout of the FXSAVE state map: one for
legacy and compatibility mode, a second format for 64-bit mode with promoted oper-
andsize, and the third format is for 64-bit mode with default operand size. Table 3-48
shows the layout of the legacy/compatibility mode state information in memory and
describes the fields in the memory image for the FXRSTOR and FXSAVE instructions.
Table 3-51 shows the layout of the 64-bit mode stat information when REX.W is set.
Table 3-52 shows the layout of the 64-bit mode stat information when REX.W is clear.
The state image referenced with an FXRSTOR instruction must have been saved
using an FXSAVE instruction or be in the same format as required by Table 3-48,
Table 3-51, or Table 3-52. Referencing a state image saved with an FSAVE, FNSAVE
instruction or incompatible field layout will result in an incorrect state restoration.
The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and
raise exceptions when loading x87 FPU state information with the FXRSTOR instruc-
tion, use an FWAIT instruction after the FXRSTOR instruction.
If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not
restore the states of the XMM and MXCSR registers. This behavior is implementation
dependent.
If the MXCSR state contains an unmasked exception with a corresponding status flag
also set, loading the register with the FXRSTOR instruction will not result in a SIMD
floating-point error condition being generated. Only the next occurrence of this
unmasked exception will result in the exception being generated.
Bits 16 through 32 of the MXCSR register are defined as reserved and should be set
to 0. Attempting to write a 1 in any of these bits from the saved state image will
result in a general protection exception (#GP) being generated.
memory image specified in the source operand. This data should have been written
to memory previously using the FXSAVE instruction, and in the same format as
required by the operating modes. The first byte of the data should be located on a
16-byte boundary. There are three distinct layout of the FXSAVE state map: one for
legacy and compatibility mode, a second format for 64-bit mode with promoted oper-
andsize, and the third format is for 64-bit mode with default operand size. Table 3-48
shows the layout of the legacy/compatibility mode state information in memory and
describes the fields in the memory image for the FXRSTOR and FXSAVE instructions.
Table 3-51 shows the layout of the 64-bit mode stat information when REX.W is set.
Table 3-52 shows the layout of the 64-bit mode stat information when REX.W is clear.
The state image referenced with an FXRSTOR instruction must have been saved
using an FXSAVE instruction or be in the same format as required by Table 3-48,
Table 3-51, or Table 3-52. Referencing a state image saved with an FSAVE, FNSAVE
instruction or incompatible field layout will result in an incorrect state restoration.
The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and
raise exceptions when loading x87 FPU state information with the FXRSTOR instruc-
tion, use an FWAIT instruction after the FXRSTOR instruction.
If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not
restore the states of the XMM and MXCSR registers. This behavior is implementation
dependent.
If the MXCSR state contains an unmasked exception with a corresponding status flag
also set, loading the register with the FXRSTOR instruction will not result in a SIMD
floating-point error condition being generated. Only the next occurrence of this
unmasked exception will result in the exception being generated.
Bits 16 through 32 of the MXCSR register are defined as reserved and should be set
to 0. Attempting to write a 1 in any of these bits from the saved state image will
result in a general protection exception (#GP) being generated.
Operation
(x87 FPU, MMX, XMM7-XMM0, MXCSR) ← Load(SRC);
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F AE /1
FXRSTOR m512byte Valid
Valid
Restore the x87 FPU, MMX, XMM,
and MXCSR register state from
m512byte.