Intel 253666-024US Manuel D’Utilisation
3-6 Vol. 2A
INSTRUCTION SET REFERENCE, A-M
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Sreg — A segment register. The segment register bit assignments are ES = 0,
CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5.
CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5.
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m32fp, m64fp, m80fp — A single-precision, double-precision, and double
extended-precision (respectively) floating-point operand in memory. These
symbols designate floating-point values that are used as operands for x87 FPU
floating-point instructions.
extended-precision (respectively) floating-point operand in memory. These
symbols designate floating-point values that are used as operands for x87 FPU
floating-point instructions.
•
m16int, m32int, m64int — A word, doubleword, and quadword integer
(respectively) operand in memory. These symbols designate integers that are
used as operands for x87 FPU integer instructions.
(respectively) operand in memory. These symbols designate integers that are
used as operands for x87 FPU integer instructions.
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ST or ST(0) — The top element of the FPU register stack.
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ST(i) — The i
th
element from the top of the FPU register stack (i ← 0 through 7).
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mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.
•
mm/m32 — The low order 32 bits of an MMX register or a 32-bit memory
operand. The 64-bit MMX registers are: MM0 through MM7. The contents of
memory are found at the address provided by the effective address computation.
operand. The 64-bit MMX registers are: MM0 through MM7. The contents of
memory are found at the address provided by the effective address computation.
•
mm/m64 — An MMX register or a 64-bit memory operand. The 64-bit MMX
registers are: MM0 through MM7. The contents of memory are found at the
address provided by the effective address computation.
registers are: MM0 through MM7. The contents of memory are found at the
address provided by the effective address computation.
•
xmm — An XMM register. The 128-bit XMM registers are: XMM0 through XMM7;
XMM8 through XMM15 are available using REX.R in 64-bit mode.
XMM8 through XMM15 are available using REX.R in 64-bit mode.
•
xmm/m32— An XMM register or a 32-bit memory operand. The 128-bit XMM
registers are XMM0 through XMM7; XMM8 through XMM15 are available using
REX.R in 64-bit mode. The contents of memory are found at the address provided
by the effective address computation.
registers are XMM0 through XMM7; XMM8 through XMM15 are available using
REX.R in 64-bit mode. The contents of memory are found at the address provided
by the effective address computation.
•
xmm/m64 — An XMM register or a 64-bit memory operand. The 128-bit SIMD
floating-point registers are XMM0 through XMM7; XMM8 through XMM15 are
available using REX.R in 64-bit mode. The contents of memory are found at the
address provided by the effective address computation.
floating-point registers are XMM0 through XMM7; XMM8 through XMM15 are
available using REX.R in 64-bit mode. The contents of memory are found at the
address provided by the effective address computation.
•
xmm/m128 — An XMM register or a 128-bit memory operand. The 128-bit XMM
registers are XMM0 through XMM7; XMM8 through XMM15 are available using
REX.R in 64-bit mode. The contents of memory are found at the address provided
by the effective address computation.
registers are XMM0 through XMM7; XMM8 through XMM15 are available using
REX.R in 64-bit mode. The contents of memory are found at the address provided
by the effective address computation.
3.1.1.3
64-bit Mode Column in the Instruction Summary Table
The “64-bit Mode” column indicates whether the opcode sequence is supported in
64-bit mode. The column uses the following notation:
64-bit mode. The column uses the following notation:
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Valid — Supported.
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Invalid — Not supported.
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N.E. — Indicates an instruction syntax is not encodable in 64-bit mode (it may
represent part of a sequence of valid instructions in other modes).
represent part of a sequence of valid instructions in other modes).