Intel 253666-024US Manuel D’Utilisation
Vol. 2A 3-11
INSTRUCTION SET REFERENCE, A-M
The addressed bit is numbered (Offset MOD 8) within the byte at address
(BitBase + (BitOffset DIV 8)) where DIV is signed division with rounding towards
negative infinity and MOD returns a positive number (see Figure 3-2).
(BitBase + (BitOffset DIV 8)) where DIV is signed division with rounding towards
negative infinity and MOD returns a positive number (see Figure 3-2).
3.1.1.8
Intel
®
C/C++ Compiler Intrinsics Equivalents Section
The Intel C/C++ compiler intrinsics equivalents are special C/C++ coding extensions that
allow using the syntax of C function calls and C variables instead of hardware regis-
ters. Using these intrinsics frees programmers from having to manage registers and
assembly programming. Further, the compiler optimizes the instruction scheduling
so that executable run faster.
The following sections discuss the intrinsics API and the MMX technology and SIMD
floating-point intrinsics. Each intrinsic equivalent is listed with the instruction
description. There may be additional intrinsics that do not have an instruction equiv-
alent. It is strongly recommended that the reader reference the compiler documen-
tation for the complete list of supported intrinsics.
ters. Using these intrinsics frees programmers from having to manage registers and
assembly programming. Further, the compiler optimizes the instruction scheduling
so that executable run faster.
The following sections discuss the intrinsics API and the MMX technology and SIMD
floating-point intrinsics. Each intrinsic equivalent is listed with the instruction
description. There may be additional intrinsics that do not have an instruction equiv-
alent. It is strongly recommended that the reader reference the compiler documen-
tation for the complete list of supported intrinsics.
Table 3-2. Range of Bit Positions Specified by Bit Offset Operands
Operand Size
Immediate BitOffset
Register BitOffset
16
0 to 15
−2
15
to 2
15
− 1
32
0 to 31
−2
31
to 2
31
− 1
64
0 to 63
−2
63
to 2
63
− 1
Figure 3-2. Memory Bit Indexing
BitBase + 1
0
7
7
7
5
0
0
BitBase − 2
0
7
7
7
5
0
0
BitBase
BitBase − 1
BitOffset ← +13
BitOffset ← −11
BitBase − 1
BitBase