Intel 253666-024US Manuel D’Utilisation

Vol. 2A 3-17

INSTRUCTION SET REFERENCE, A-M

3.1.1.15   SIMD Floating-Point Exceptions Section

The “SIMD Floating-Point Exceptions” section lists exceptions that can occur when an 
SSE/SSE2/SSE3 floating-point instruction is executed. All of these exception condi-
tions result in a SIMD floating-point error exception (#XM, vector number 19) being 
generated. Table 3-5 associates a one-letter mnemonic with the corresponding 
exception name. For a detailed description of these exceptions, refer to ”SSE and 
SSE2 Exceptions”, in Chapter 11 of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1.

3.1.1.16   Compatibility Mode Exceptions Section

This section lists exception that occur within compatibility mode.

3.1.1.17   64-Bit Mode Exceptions Section

This section lists exception that occur within 64-bit mode.

Table 3-4.  x87 FPU Floating-Point Exceptions

Mnemonic

Name

Source

#IS

#IA

Floating-point invalid operation:
- Stack overflow or underflow
- Invalid arithmetic operation

- x87 FPU stack overflow or underflow
- Invalid FPU arithmetic operation

#Z

Floating-point divide-by-zero

Divide-by-zero

#D

Floating-point denormal operand

Source operand that is a denormal number

#O

Floating-point numeric overflow

Overflow in result

#U

Floating-point numeric underflow

Underflow in result

#P

Floating-point inexact result 

(precision)

Inexact result (precision)

Table 3-5.  SIMD Floating-Point Exceptions

Mnemonic

Name

Source

#I

Floating-point invalid operation

Invalid arithmetic operation or source operand

#Z

Floating-point divide-by-zero

Divide-by-zero

#D

Floating-point denormal operand Source operand that is a denormal number

#O

Floating-point numeric overflow

Overflow in result

#U

Floating-point numeric underflow Underflow in result

#P

Floating-point inexact result

Inexact result (precision)