Intel 253666-024US Manuel D’Utilisation
3-596 Vol. 2A
MONITOR—Set Up Monitor Address
INSTRUCTION SET REFERENCE, A-M
MONITOR—Set Up Monitor Address
Description
The MONITOR instruction arms address monitoring hardware using an address spec-
ified in EAX (the address range that the monitoring hardware checks for store opera-
tions can be determined by using CPUID). A store to an address within the specified
address range triggers the monitoring hardware. The state of monitor hardware is
used by MWAIT.
The content of EAX is an effective address. By default, the DS segment is used to
create a linear address that is monitored. Segment overrides can be used.
ECX and EDX are also used. They communicate other information to MONITOR. ECX
specifies optional extensions. EDX specifies optional hints; it does not change the
architectural behavior of the instruction. For the Pentium 4 processor (family 15,
model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by
the processor; undefined extensions in ECX raises a general protection fault.
The address range must use memory of the write-back type. Only write-back
memory will correctly trigger the monitoring hardware. Additional information on
determining what address range to use in order to prevent false wake-ups is
described in Chapter 7, “Multiple-Processor Management” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A.
The MONITOR instruction is ordered as a load operation with respect to other
memory transactions. The instruction can be used at all privilege levels and is subject
to the permission checking and faults associated with a byte load. Like a load,
MONITOR sets the A-bit but not the D-bit in page tables.
The MONITOR CPUID feature flag (ECX bit 3; CPUID executed EAX = 1) indicates the
availability of MONITOR and MWAIT in the processor. When set, the unconditional
execution of MONITOR is supported at privilege levels 0; conditional execution is
supported at privilege levels 1 through 3 (test for the appropriate support before
unconditional use). The operating system or system BIOS may disable this instruc-
tion by using the IA32_MISC_ENABLES MSR; disabling MONITOR clears the CPUID
feature flag and causes execution to generate an illegal opcode exception.
The instruction’s operation is the same in non-64-bit modes and 64-bit mode.
ified in EAX (the address range that the monitoring hardware checks for store opera-
tions can be determined by using CPUID). A store to an address within the specified
address range triggers the monitoring hardware. The state of monitor hardware is
used by MWAIT.
The content of EAX is an effective address. By default, the DS segment is used to
create a linear address that is monitored. Segment overrides can be used.
ECX and EDX are also used. They communicate other information to MONITOR. ECX
specifies optional extensions. EDX specifies optional hints; it does not change the
architectural behavior of the instruction. For the Pentium 4 processor (family 15,
model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by
the processor; undefined extensions in ECX raises a general protection fault.
The address range must use memory of the write-back type. Only write-back
memory will correctly trigger the monitoring hardware. Additional information on
determining what address range to use in order to prevent false wake-ups is
described in Chapter 7, “Multiple-Processor Management” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A.
The MONITOR instruction is ordered as a load operation with respect to other
memory transactions. The instruction can be used at all privilege levels and is subject
to the permission checking and faults associated with a byte load. Like a load,
MONITOR sets the A-bit but not the D-bit in page tables.
The MONITOR CPUID feature flag (ECX bit 3; CPUID executed EAX = 1) indicates the
availability of MONITOR and MWAIT in the processor. When set, the unconditional
execution of MONITOR is supported at privilege levels 0; conditional execution is
supported at privilege levels 1 through 3 (test for the appropriate support before
unconditional use). The operating system or system BIOS may disable this instruc-
tion by using the IA32_MISC_ENABLES MSR; disabling MONITOR clears the CPUID
feature flag and causes execution to generate an illegal opcode exception.
The instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
OF 01 C8
MONITOR
Valid
Valid
Sets up a linear address range to be
monitored by hardware and activates
the monitor. The address range should
be a write-back memory caching type.
The default address is DS:EAX.