Intel 253666-024US Manuel D’Utilisation
3-616 Vol. 2A
MOVD/MOVQ—Move Doubleword/Move Quadword
INSTRUCTION SET REFERENCE, A-M
MOVD/MOVQ—Move Doubleword/Move Quadword
Description
Copies a doubleword from the source operand (second operand) to the destination
operand (first operand). The source and destination operands can be general-
purpose registers, MMX technology registers, XMM registers, or 32-bit memory loca-
tions. This instruction can be used to move a doubleword to and from the low double-
word of an MMX technology register and a general-purpose register or a 32-bit
memory location, or to and from the low doubleword of an XMM register and a
general-purpose register or a 32-bit memory location. The instruction cannot be
used to transfer data between MMX technology registers, between XMM registers,
between general-purpose registers, or between memory locations.
When the destination operand is an MMX technology register, the source operand is
written to the low doubleword of the register, and the register is zero-extended to 64
bits. When the destination operand is an XMM register, the source operand is written
to the low doubleword of the register, and the register is zero-extended to 128 bits.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R
prefix permits access to additional registers (R8-R15). Use of the REX.W prefix
promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.
operand (first operand). The source and destination operands can be general-
purpose registers, MMX technology registers, XMM registers, or 32-bit memory loca-
tions. This instruction can be used to move a doubleword to and from the low double-
word of an MMX technology register and a general-purpose register or a 32-bit
memory location, or to and from the low doubleword of an XMM register and a
general-purpose register or a 32-bit memory location. The instruction cannot be
used to transfer data between MMX technology registers, between XMM registers,
between general-purpose registers, or between memory locations.
When the destination operand is an MMX technology register, the source operand is
written to the low doubleword of the register, and the register is zero-extended to 64
bits. When the destination operand is an XMM register, the source operand is written
to the low doubleword of the register, and the register is zero-extended to 128 bits.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R
prefix permits access to additional registers (R8-R15). Use of the REX.W prefix
promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F 6E /r
MOVD mm, r/m32 Valid
Valid
Move doubleword from
r/m32 to mm.
REX.W + 0F 6E /r
MOVQ mm, r/m64 Valid
N.E.
Move quadword from r/m64
to mm.
0F 7E /r
MOVD r/m32, mm Valid
Valid
Move doubleword from mm
to r/m32.
REX.W + 0F 7E /r
MOVQ r/m64, mm Valid
N.E.
Move quadword from mm to
r/m64.
66 0F 6E /r
MOVD xmm,
r/m32
Valid
Valid
Move doubleword from
r/m32 to xmm.
66 REX.W 0F 6E /r
MOVQ xmm,
r/m64
Valid
N.E.
Move quadword from r/m64
to xmm.
66 0F 7E /r
MOVD r/m32,
xmm
Valid
Valid
Move doubleword from
xmm register to r/m32.
66 REX.W 0F 7E /r
MOVQ r/m64,
xmm
Valid
N.E.
Move quadword from xmm
register to r/m64.