Intel 253666-024US Manuel D’Utilisation
Vol. 2A 3-625
INSTRUCTION SET REFERENCE, A-M
MOVDQU—Move Unaligned Double Quadword
MOVDQU—Move Unaligned Double Quadword
Description
Moves a double quadword from the source operand (second operand) to the destina-
tion operand (first operand). This instruction can be used to load an XMM register
from a 128-bit memory location, to store the contents of an XMM register into a
128-bit memory location, or to move data between two XMM registers. When the
source or destination operand is a memory operand, the operand may be unaligned
on a 16-byte boundary without causing a general-protection exception (#GP) to be
generated.
To move a double quadword to or from memory locations that are known to be
aligned on 16-byte boundaries, use the MOVDQA instruction.
While executing in 16-bit addressing mode, a linear address for a 128-bit data access
that overlaps the end of a 16-bit segment is not allowed and is defined as reserved
behavior. A specific processor implementation may or may not generate a general-
protection exception (#GP) in this situation, and the address that spans the end of
the segment may or may not wrap around to the beginning of the segment.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
tion operand (first operand). This instruction can be used to load an XMM register
from a 128-bit memory location, to store the contents of an XMM register into a
128-bit memory location, or to move data between two XMM registers. When the
source or destination operand is a memory operand, the operand may be unaligned
on a 16-byte boundary without causing a general-protection exception (#GP) to be
generated.
To move a double quadword to or from memory locations that are known to be
aligned on 16-byte boundaries, use the MOVDQA instruction.
While executing in 16-bit addressing mode, a linear address for a 128-bit data access
that overlaps the end of a 16-bit segment is not allowed and is defined as reserved
behavior. A specific processor implementation may or may not generate a general-
protection exception (#GP) in this situation, and the address that spans the end of
the segment may or may not wrap around to the beginning of the segment.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST ← SRC;
Intel C/C++ Compiler Intrinsic Equivalent
MOVDQU void _mm_storeu_si128 ( __m128i *p, __m128i a)
MOVDQU __m128i _mm_loadu_si128 ( __m128i *p)
MOVDQU __m128i _mm_loadu_si128 ( __m128i *p)
SIMD Floating-Point Exceptions
None.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 6F /r
MOVDQU xmm1,
xmm2/m128
Valid
Valid
Move unaligned double
quadword from xmm2/m128 to
xmm1.
F3 0F 7F /r
MOVDQU xmm2/m128,
xmm1
Valid
Valid
Move unaligned double
quadword from xmm1 to
xmm2/m128.