Intel 253666-024US Manuel D’Utilisation

3-698 Vol. 2A

MULPD—Multiply Packed Double-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

MULPD—Multiply Packed Double-Precision Floating-Point Values

Description

Performs a SIMD multiply of the two packed double-precision floating-point values 
from the source operand (second operand) and the destination operand (first 
operand), and stores the packed double-precision floating-point results in the desti-
nation operand. The source operand can be an XMM register or a 128-bit memory 
location. The destination operand is an XMM register. See Figure 11-3 in the Intel® 
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustra-
tion of a SIMD double-precision floating-point operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional 
registers (XMM8-XMM15).

Operation

DEST[63:0]  ← DEST[63:0]

 ∗

 SRC[63:0];

DEST[127:64]  ← DEST[127:64]

 ∗

 SRC[127:64];

Intel C/C++ Compiler Intrinsic Equivalent

MULPD

__m128d _mm_mul_pd (m128d a, m128d b)

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS, 

ES, FS or GS segments.

If a memory operand is not aligned on a 16-byte boundary, 

regardless of segment.

#SS(0) 

For an illegal address in the SS segment. 

#PF(fault-code) 

For a page fault.

#NM

If CR0.TS[bit 3] = 1. 

#XM 

If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1. 

Opcode

Instruction

64-Bit 

Mode

Compat/

Leg Mode

Description

66 0F 59 /r MULPD xmm1, 

Valid

Valid

Multiply packed double-precision 

floating-point values in xmm2/m128 by 

xmm1.