Samsung S3C2440A Manuel D’Utilisation
S3C2440A RISC MICROPROCESSOR
PWM TIMER
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PWM TIMER
OVERVIEW
The S3C2440A has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4
has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large
current device.
has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large
current device.
The timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler. Each timer has a
clock divider, which generates 5 different divided signals (1/2, 1/4, 1/8, 1/16, and TCLK). Each timer block receives
its own clock signals from the clock divider, which receives the clock from the corresponding 8-bit prescaler. The
8-bit prescaler is programmable and divides the PCLK according to the loading value, which is stored in TCFG0
and TCFG1 registers.
clock divider, which generates 5 different divided signals (1/2, 1/4, 1/8, 1/16, and TCLK). Each timer block receives
its own clock signals from the clock divider, which receives the clock from the corresponding 8-bit prescaler. The
8-bit prescaler is programmable and divides the PCLK according to the loading value, which is stored in TCFG0
and TCFG1 registers.
The timer count buffer register (TCNTBn) has an initial value which is loaded into the down-counter when the timer
is enabled. The timer compare buffer register (TCMPBn) has an initial value which is loaded into the compare
register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn
makes the timer generate a stable output when the frequency and duty ratio are changed.
is enabled. The timer compare buffer register (TCMPBn) has an initial value which is loaded into the compare
register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn
makes the timer generate a stable output when the frequency and duty ratio are changed.
Each timer has its own 16-bit down counter, which is driven by the timer clock. When the down counter reaches
zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed.
When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down
counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of
TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter.
zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed.
When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down
counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of
TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter.
The value of TCMPBn is used for pulse width modulation (PWM). The timer control logic changes the output level
when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the
compare register determines the turn-on time (or turn-off time) of a PWM output.
when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the
compare register determines the turn-on time (or turn-off time) of a PWM output.
FEATURE
— Five 16-bit timers
— Two 8-bit prescalers & Two 4-bit divider
— Programmable duty control of output waveform (PWM)
— Auto reload mode or one-shot pulse mode
— Dead-zone generator