Intel 253668-032US Manuel D’Utilisation
Vol. 3 3-11
PROTECTED-MODE MEMORY MANAGEMENT
For a program to access a segment, the segment selector for the segment must have
been loaded in one of the segment registers. So, although a system can define thou-
sands of segments, only 6 can be available for immediate use. Other segments can
be made available by loading their segment selectors into these registers during
program execution.
been loaded in one of the segment registers. So, although a system can define thou-
sands of segments, only 6 can be available for immediate use. Other segments can
be made available by loading their segment selectors into these registers during
program execution.
Every segment register has a “visible” part and a “hidden” part. (The hidden part is
sometimes referred to as a “descriptor cache” or a “shadow register.”) When a
segment selector is loaded into the visible part of a segment register, the processor
also loads the hidden part of the segment register with the base address, segment
limit, and access control information from the segment descriptor pointed to by the
segment selector. The information cached in the segment register (visible and
hidden) allows the processor to translate addresses without taking extra bus cycles
to read the base address and limit from the segment descriptor. In systems in which
multiple processors have access to the same descriptor tables, it is the responsibility
of software to reload the segment registers when the descriptor tables are modified.
If this is not done, an old segment descriptor cached in a segment register might be
used after its memory-resident version has been modified.
Two kinds of load instructions are provided for loading the segment registers:
1. Direct load instructions such as the MOV, POP, LDS, LES, LSS, LGS, and LFS
sometimes referred to as a “descriptor cache” or a “shadow register.”) When a
segment selector is loaded into the visible part of a segment register, the processor
also loads the hidden part of the segment register with the base address, segment
limit, and access control information from the segment descriptor pointed to by the
segment selector. The information cached in the segment register (visible and
hidden) allows the processor to translate addresses without taking extra bus cycles
to read the base address and limit from the segment descriptor. In systems in which
multiple processors have access to the same descriptor tables, it is the responsibility
of software to reload the segment registers when the descriptor tables are modified.
If this is not done, an old segment descriptor cached in a segment register might be
used after its memory-resident version has been modified.
Two kinds of load instructions are provided for loading the segment registers:
1. Direct load instructions such as the MOV, POP, LDS, LES, LSS, LGS, and LFS
instructions. These instructions explicitly reference the segment registers.
2. Implied load instructions such as the far pointer versions of the CALL, JMP, and
RET instructions, the SYSENTER and SYSEXIT instructions, and the IRET, INTn,
INTO and INT3 instructions. These instructions change the contents of the CS
register (and sometimes other segment registers) as an incidental part of their
operation.
INTO and INT3 instructions. These instructions change the contents of the CS
register (and sometimes other segment registers) as an incidental part of their
operation.
The MOV instruction can also be used to store visible part of a segment register in a
general-purpose register.
general-purpose register.
Figure 3-7. Segment Registers
CS
SS
DS
ES
FS
GS
Segment Selector
Base Address, Limit, Access Information
Visible Part
Hidden Part