Intel 253668-032US Manuel D’Utilisation
Vol. 3 16-15
DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER
in the last branch record (LBR) stack. For more information, see the Section
16.5.1, “LBR Stack”.
16.5.1, “LBR Stack”.
•
BTF (single-step on branches) flag (bit 1) — When set, the processor treats
the TF flag in the EFLAGS register as a “single-step on branches” flag rather than
a “single-step on instructions” flag. This mechanism allows single-stepping the
processor on taken branches, interrupts, and exceptions. See Section 16.4.3,
“Single-Stepping on Branches, Exceptions, and Interrupts,” for more information
about the BTF flag.
a “single-step on instructions” flag. This mechanism allows single-stepping the
processor on taken branches, interrupts, and exceptions. See Section 16.4.3,
“Single-Stepping on Branches, Exceptions, and Interrupts,” for more information
about the BTF flag.
•
TR (trace message enable) flag (bit 6) — When set, branch trace messages
are enabled. When the processor detects a taken branch, interrupt, or exception;
it sends the branch record out on the system bus as a branch trace message
(BTM). See Section 16.4.4, “Branch Trace Messages,” for more information about
the TR flag.
are enabled. When the processor detects a taken branch, interrupt, or exception;
it sends the branch record out on the system bus as a branch trace message
(BTM). See Section 16.4.4, “Branch Trace Messages,” for more information about
the TR flag.
•
BTS (branch trace store) flag (bit 7) — When set, the flag enables BTS
facilities to log BTMs to a memory-resident BTS buffer that is part of the DS save
area. See Section 16.4.9, “BTS and DS Save Area.”
facilities to log BTMs to a memory-resident BTS buffer that is part of the DS save
area. See Section 16.4.9, “BTS and DS Save Area.”
•
BTINT (branch trace interrupt) flag (bit 8) — When set, the BTS facilities
generate an interrupt when the BTS buffer is full. When clear, BTMs are logged to
the BTS buffer in a circular fashion. See Section 16.4.5, “Branch Trace Store (BTS),”
for a description of this mechanism.
generate an interrupt when the BTS buffer is full. When clear, BTMs are logged to
the BTS buffer in a circular fashion. See Section 16.4.5, “Branch Trace Store (BTS),”
for a description of this mechanism.
•
BTS_OFF_OS (branch trace off in privileged code) flag (bit 9) — When set,
BTS or BTM is skipped if CPL is 0. See Section 16.7.2.
BTS or BTM is skipped if CPL is 0. See Section 16.7.2.
•
BTS_OFF_USR (branch trace off in user code) flag (bit 10) — When set,
BTS or BTM is skipped if CPL is greater than 0. See Section 16.7.2.
BTS or BTM is skipped if CPL is greater than 0. See Section 16.7.2.
Figure 16-3. IA32_DEBUGCTL MSR for Processors based
on Intel Core
microarchitecture
31
TR — Trace messages enable
BTINT — Branch trace interrupt
BTF — Single-step on branches
LBR — Last branch/interrupt/exception
LBR — Last branch/interrupt/exception
Reserved
8 7 6 5 4 3 2 1 0
BTS — Branch trace store
Reserved
9
10
BTS_OFF_OS — BTS off in OS
BTS_OFF_USR — BTS off in user code
FREEZE_LBRS_ON_PMI
FREEZE_PERFMON_ON_PMI
11
12
14
FREEZE_WHILE_SMM_EN