Intel 253668-032US Manuel D’Utilisation

16-42 Vol. 3

DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER

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Debug store (DS) feature flag (bit 21), returned by the CPUID
instruction — Indicates that the processor provides the debug store (DS)
mechanism, which allows BTMs to be stored in a memory-resident BTS buffer.
See Section 16.4.5, “Branch Trace Store (BTS).”

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Last Branch Record (LBR) Stack — The LBR stack consists of 8 MSRs
(MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’
address, bits 63-32 hold the ‘to’ address (MSR addresses start at 40H). See
Figure 16-15.

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Last Branch Record Top-of-Stack (TOS) Pointer — The TOS Pointer MSR
contains a 3-bit pointer (bits 2-0) to the MSR in the LBR stack that contains the
most recent branch, interrupt, or exception recorded. For Intel Core Solo and
Intel Core Duo processors, this MSR is located at register address 01C9H.

For compatibility, the Intel Core Solo and Intel Core Duo processors provide two 32-
bit MSRs (the MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that duplicate
functions of the LastExceptionToIP and LastExceptionFromIP MSRs found in P6 family
processors.
For details, see Section 16.7, “Last Branch, Interrupt, and Exception Recording
(Processors based on Intel NetBurst

Microarchitecture),” and Appendix B.6, “MSRs

Figure 16-14. IA32_DEBUGCTL MSR for Intel Core Solo

and Intel Core

Duo Processors

TR — Trace messages enable