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FH8065501516761
Volume 2—Power Management—C2000 Product Family
Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
152
Order Number: 330061-002US
9
Power Management
The SoC is a server-class component and provides dynamic power management that fit
a number of usages like storage and networking. As the technology changes and the
number of cores per node and per module changes, this places a requirement to find
the best approach to manage the TDP power of the node/module with respect to the
available power budget.
9.1
Overview
The power management control is comprised of a number of Intel
®
proprietary
mechanisms. The power management signal interface to the rest of the platform is
through the Power Management Controller (PMC) block in the Platform Controller Unit
(PCU). In some areas, this chapter refers to this distributed function as the SoC Power
Management Unit (PMU).
An external, board-level Baseboard Management Controller (BMC) or some other
embedded controller, is required to manage the platform power planes, power-on,
sleep states, and reset signaling. This chapter refers to the BMC or Embedded
Controller (EC). The EC interfaces with the SoC internal fabric to perform its
management functions.
The SoC power management is responsible for the following tasks:
• Managing the internal power wells voltages
• Communicating with the EC
• Resetting sequencing
• Managing processor C-states
• Managing L2 cache dynamic sizing
• Managing Sleep-state entry sequences
• Managing DDR3 power management and RComp routines
• Controlling Low Pin Count (LPC) interface clock
• Directing processor thermal management
• Interfacing with the BIOS and the operating system software
• Managing Intel
• Communicating with the EC
• Resetting sequencing
• Managing processor C-states
• Managing L2 cache dynamic sizing
• Managing Sleep-state entry sequences
• Managing DDR3 power management and RComp routines
• Controlling Low Pin Count (LPC) interface clock
• Directing processor thermal management
• Interfacing with the BIOS and the operating system software
• Managing Intel
®
Turbo Boost Technology and RAPL control
Table 9-1.
References
Reference
Revision
Date
Description
ACPI
Specification
5.0
DEC 2011
Advanced Configuration and Power Interface Specification
,
Revision 5.0
VR12/IMVP7
Specification
1.61
OCT 2011
VR12/IMVP7 Pulse Width Modulation
, Revision 1.61
(Intel Document Number 397113)
VR12/IMVP7
Protocol
1.5
AUG 2010
VR12/IMVP7 SVID Protocol
, Revision 1.5
(Intel Document Number 456098)