Intel E3815 FH8065301567411 Fiche De Données
Codes de produits
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
161
NOTES:
1.
Excluding static ground shift of 50 mV.
2.
∆V
CMRX(HF)
is the peak amplitude of a sine wave superimposed on the receiver inputs.
3.
For higher bit rates a 14 pF capacitor is needed to meet the common-mode return loss specification.
4.
Voltage difference compared to the DC average common-mode potential.
5.
Time-voltage integration of a spike above V
IL
when in the LP-0 state or below V
IH
when in the LP-1
state.
6.
An impulse spike less than this will not change the receiver state.
7.
In addition to the required glitch rejection, designers shall ensure rejection of known RF-interference.
8.
An input pulse greater than this will toggle the output
9.
Improves on DPHY specification, which requires 100 mV maximum.
NOTE:
1
The minimum UI shall not be violated for any single bit period, that is, any DDR half cycle
within a data burst.
S
CDRX
differential to common-mode
–
–
-26
dB
From 0 to
fMAX
(1.33Ghz)
MIPI LP-Receiver Mode
e
spike
Input pulse rejection
–
–
300
V*ps
5, 6, 7
T
MIN-RX
Minimum pulse width response
20
–
–
ns
8
V
INT
Peak interference amplitude
–
–
200
mV
f
INT
Interference frequency
450
–
–
MHz
Table 116. MIPI-CSI-2 Receiver Characteristics (Sheet 2 of 2)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Figure 37. Input Glitch Rejection of Low-Power Receivers
Table 117. MIPI-CSI-2 Clock Signal Specification
Symbol
Clock Parameter
Min.
Typ.
Max.
Unit
Note
s
UI
INST
UI Instantaneous (In 1 or
2 or 3 or 4 Lane
configuration)
2 or 3 or 4 Lane
configuration)
1
(1Gbps/
500Mhz)
(1Gbps/
500Mhz)
2.77
(163 Mbps/
80Mhz)
80Mhz)
ns
1
I n p u t
O u t p u t
e
S P I K E
V
I L
V
I H
e
S P I K E
T
M I N I - R X
2 * T
L P X
T
M I N I - R X
2 * T
L P X