Intel E3815 FH8065301567411 Fiche De Données
Codes de produits
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2363
18.8.16
Intel-Specific USB2 SMI (ISU2SMI)—Offset 70h
Access Method
Default: 00000000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SM
Io
nPO1_0
SMIonP
MC
SR_0
SMIo
nAsyn
c_0
SMIonP
er
iod
ic_0
SMIonC
F_0
S
M
IonH
CH
alte
d_0
SMIonH
C
R
st_0
SMIonPOE
n_0
SMIon
PMS
CRE
n
_0
S
M
IonAs
yncE
n
_0
SMIo
nP
er
io
dicE
n_0
SMIon
C
FE
n_0
SMIonH
C
H
alte
dE
n_0
SMIon
H
C
R
stE
n
_0
Bit
Range
Default &
Access
Field Name (ID): Description
31:22
0h
RWC
SMI on PortOwner (SMIonPO1_0):
Bits 29:22 correspond to the Port Owner bits for
ports 1 (22) through 8 (29). These bits are set to '1' whenever the associated Port
Owner bits transition from 0-)1 or 1-)0. Software clears these bits by writing a one. This
register is implemented in the Suspend Well. This register is only reset by the resume
power well going low. It is not reset by the core power well going low or by a D3-to-D0
state transition
Power Well:
Resume
21
0b
RWC
SMI on PMCSR (SMIonPMCSR_0):
This bit is set to '1' whenever software modifies
the Power State bits in the Power Management Control/Status register. This register is
implemented in the Suspend Well. This register is only reset by the resume power well
going low. It is not reset by the core power well going low or by a D3-to-D0 state
transition
Power Well:
Resume
20
0b
RWC
SMI on Async (SMIonAsync_0):
This bit is set to '1' whenever the Async Schedule
Enable bit transitions from 1-)0 or 0-)1. This register is implemented in the Suspend
Well. This register is only reset by the resume power well going low. It is not reset by
the core power well going low or by a D3-to-D0 state transition
Power Well:
Resume
19
0b
RWC
SMI on Periodic (SMIonPeriodic_0):
This bit is set to '1' whenever the Periodic
Schedule Enable bit transitions from 1-)0 or 0-)1. This register is implemented in the
Suspend Well. This register is only reset by the resume power well going low. It is not
reset by the core power well going low or by a D3-to-D0 state transition
Power Well:
Resume
18
0b
RWC
SMI on CF (SMIonCF_0):
This bit is set to '1' whenever the Configure Flag transitions
from 1-)0 or 0-)1. This register is implemented in the Suspend Well. This register is only
reset by the resume power well going low. It is not reset by the core power well going
low or by a D3-to-D0 state transition
Power Well:
Resume
17
0b
RWC
SMI on HCHalted (SMIonHCHalted_0):
This bit is set to '1' whenever HCHalted
transitions to '1' as a result of the Run/Stop bit being cleared. This register is only reset
by the resume power well going low. It is not reset by the core power well going low or
by a D3-to-D0 state transition
Power Well:
Resume