Intel E3815 FH8065301567411 Fiche De Données
Codes de produits
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2633
19.6.252 OEVT—Offset CC08h
Value After Reset: 0x0 OTG Events Register
Access Method
Default: 80000000h
3
0h
RW
SesReq:
Session Request: n 1'b0: No session request n 1'b1: Session request The
application sets this bit to initiate a session request on the USB. Writing 1'b1 to this field
will trigger the core to send SRP (data line pulsing) on PHY interface. In the absence of
OEVT.OTGBDevSessVldDetEvnt after a session request, the application must wait for
atleast TB_SRP_FAIL time (6 secs) before initiating another session request. This field
returns 1'b0 when read.
2
0h
RW
TermSelDLPulse:
TermSel DLine Pulsing Selection: This bit selects utmi_termselect to
drive data line pulse during SRP. n 1'b0: Data line pulsing using utmi_txvalid (default). n
1'b1: Data line pulsing using utmi_termsel.
1
0h
RW
DevSetHNPEn:
Device Set RSP/HNP Enable: n 1'b0: RSP/HNP is not enabled in the
application n 1'b1: RSP/HNP is enabled in the application The application sets this bit in
the following scenario: n In HS/FS mode, when it successfully receives a
SetFeature.SetHNPEnable command from the connected USB host. n In SS mode, when
it has sent a b3_ntf_hst_rel to the A-device, or the A-device has sent an
a3_ntf_host_req. Note: The terminology RSP is used when the core is operating in SS
mode, and HNP is used when the core is operating in non-SS mode.
0
0h
RW
HstSetHNPEn:
Host Set RSP/HNP Enable: n 1'b0: Host Set RSP/HNP is not enabled n
1'b1: Host Set RSP/HNP is enabled The application sets this bit in the following scenario:
n In HS/FS mode, when it has successfully enabled HNP (using the
SetFeature.SetHNPEnable command) from the connected device. n In SS mode, when it
has successfully enabled b3_rsp_enable feature in RSP-capable Device using SetFeature
command while operating as an A-Host, or when it has received a b3_ntf_hst_rel
through SetFeature command while operating as A-peripheral. Note: The terminology
RSP is used when the core is operating in SS mode, and HNP is used when the core is
operating in non-SS mode.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
De
vice
Mode
RS
VD0
OTG
C
o
n
ID
S
ts
C
h
n
g
E
vn
t
RS
VD1
O
TGADevBHo
stE
n
dE
vnt
O
TGADevHostE
vnt
O
TGA
DevH
NPCh
ngE
vnt
O
TGAD
evS
RP
D
etE
vnt
O
TGADevSessE
ndD
etE
vnt
RS
VD2
O
TGBDevBHo
stE
n
dE
vnt
O
TGBDevH
NPCh
ngE
vnt
O
TGBDevSess
V
ldD
etE
vnt
O
TGBDevVB
U
S
C
h
n
gE
vnt
RS
VD3
BSesV
ld
Hs
tNeg
Sts
Se
sR
eq
St
s
OE
V
T
E
rro
r
Bit
Range
Default &
Access
Description
31
1h
RO
DeviceMode:
Device Mode: Indicates whether the device is in A-device or B-device
mode based on utmiotg_iddig n 1'b0: A-Device mode n1'b1: B-Device mode The rest of
the OTG Event Information bits (OTGxxxxEvtInfo) in OEVT register will be based on the
contents of this field.