Intel E3815 FH8065301567411 Fiche De Données

Codes de produits
FH8065301567411
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PCU – iLB – Real Time Clock (RTC)
Intel
®
 Atom™ Processor E3800 Product Family
4546
Datasheet
36.3.2.1
Using ILB_RTC_TEST# to Clear the RTC CMOS RAM
A jumper on ILB_RTC_TEST# can be used to clear CMOS values. When 
ILB_RTC_TEST# is low, the GEN_PMCON1.RPS register bit will be set. BIOS can 
monitor the state of this bit, and manually clear the RTC CMOS array once the system 
is booted. The normal position will cause ILB_RTC_TEST# to be pulled up through a 
weak pull-up resistor. This ILB_RTC_TEST# jumper technique allows the jumper to be 
moved and then replaced—all while the system is powered off. Then, once booted, the 
GEN_PMCON1.RPS bit can be detected in the set state.
36.3.3
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS should detect the 
setting of this GPI on system boot-up, and manually clear the CMOS array.
Note:
The GPI strap technique to clear CMOS requires multiple steps to implement. The 
system is booted with the jumper in new position, then powered back down. The 
jumper is replaced back to the normal position, then the system is rebooted again.
Warning: Do not implement a jumper on RTC_VCC to clear CMOS.
36.3.4
Clearing Battery Backed RTC Registers
Clearing Battery Backed RTC Registers in an SoC based platform can be done by using 
a jumper on ILB_RTC_RST#. Implementations should not attempt to clear the registers 
by using a jumper to pull RTC_VCC low. A jumper on ILB_RTC_RST# pulled to ground 
can be used to reset the state of those Battery Backed RTC Register configurations bit 
that reside in the RTC power well to their default state. 
 shows which bits are 
set to their default state when ILB_RTC_RST# is asserted low.
Table 326. Register Bits Reset by ILB_RTC_RST# Assertion  (Sheet 1 of 2)
Register Bit
Bit(s)
Default State
RCRB_GENERAL_CONTROL.TS
1
xb
GEN_PMCON1.PME_B0_S5_DIS
15
0b
GEN_PMCON1.WOL_EN_OVRD
13
0b
GEN_PMCON1.DIS_SLP_X_STRCH_SUS_UP
12
0b
GEN_PMCON1.RTC Reserved
8
0b
GEN_PMCON1.SWSMI_RATESEL
7:6
00b
GEN_PMCON1.S4MAW
5:4
00b
GEN_PMCON1.S4ASE
3
0b
GEN_PMCON1.AG3E
0
0b
PM1_STS_EN.RTC_EN
26
0b
PM1_STS_EN.PWRBTNOR_STS
11
0b