Intel E3815 FH8065301567411 Fiche De Données

Intel

®

 Atom™ Processor E3800 Product Family

862

Datasheet

Display FIFO Watermark1 Control 4

Default: 00040404h

15:13

0b

RW

Reserved.

12

0b

RW

This field is the high 

order bit for Display B FIFO WM1. Combined with lower order 8-bit Display B FIFO WM1, 

it forms a 9-bit Display B FIFO WM1 pointer. Number in 64Bs of space in FIFO above 

which the Display A Stream will generate requests to Memory (Value should be as 

recommended in the high priority bandwidth analysis spreadsheet). 

11:9

0b

RW

Reserved.

8

0b

RW

This field is the high order bit for 

Sprite B FIFO WM1. Combined with lower order 8-bit Sprite B FIFO WM1, it forms a 9-bit 

Sprite B FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display A 

Stream will generate requests to Memory (Value should be as recommended in the high 

priority bandwidth analysis spreadsheet). 

7:5

0b

RW

MBZ

4

0b

RW

This field is the high order bit for 

Sprite A FIFO WM1. Combined with lower order 8-bit Sprite A FIFO WM1, it forms a 9-bit 

Sprite A FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display A 

Stream will generate requests to Memory (Value should be as recommended in the high 

priority bandwidth analysis spreadsheet). 

3:1

0b

RW

MBZ

0

0b

RW

This field is the high 

order bit for Display A FIFO WM1. Combined with lower order 8-bit Display A FIFO WM1, 

it forms a 9-bit Display A FIFO WM1 pointer. Number in 64Bs of space in FIFO above 

which the Display A Stream will generate requests to Memory (Value should be as 

recommended in the high priority bandwidth analysis spreadsheet). 

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h