Intel E3815 FH8065301567411 Fiche De Données
Codes de produits
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2845
21.11.8
reg_IPCX_type (IPCX)—Offset 38h
The Inter-process Status and Message register for IA-32 contains a message sent from
the IA-32 CPU to LPE. The format of the CPU message bits (61:0) is not defined in the
HW specs. It is defined in the LPE Firmware specifications. The message may contain
optional data fields stored in the shared memory region (mailbox). When the message
is written in this register, the software must set bit 63 to indicate that the IPCIA is not
empty. Setting Busy also asserts interrupt request to LPE if the interrupt is enabled in
the IMRLPEIA. After LPE reads the message code from the register, it must perform a
write with bit 63 cleared. The IA-32 CPU must not attempt to write into IPCIA if bit 63
is set.
Access Method
Default: 0000000000000000h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
IA
_L
PE_
IPC_
R
equ
est
_M
ask
IA_
LP
E
_I
PC
_D
o
n
e_
M
ask
Bit
Range
Default &
Access
Description
63:2
0b
RO
RSVD0:
Reserved
1
0b
RW
IA_LPE_IPC_Request_Mask:
IPCIA interrupt Enable to LPE
0
0b
RW
IA_LPE_IPC_Done_Mask:
IPCLPEIA interrupt Enable to LPE
Type:
Memory Mapped I/O Register
(Size: 64 bits)
IPCX:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IA
_LPE_
B
USY
LP
E
_
IA
_DON
E
IA_
LP
E
_M
SG
Bit
Range
Default &
Access
Description
63
0b
RW
IA_LPE_BUSY:
Busy. When this bit is cleared, the LPE Ready to accept a message