Texas Instruments TMS320DM644x Manuel D’Utilisation
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Start
bit
End
bit
CMD
Data
CLK
1 transfer
source bit
2 CRC
bytes
2.4
Data Flow in the Input/Output FIFO
Peripheral Architecture
Figure 6. MMC/SD Mode Read Sequence Timing Diagram
Table 3. MMC/SD Mode Read Sequence
Portion of the
Sequence
Sequence
Description
RD CMD
Read command: A 6-byte READ_SINGLE_BLOCK command token is sent from the ARM to the card.
CMD RSP
Command response: The card sends a response of type R1 to acknowledge the READ_SINGLE_BLOCK
command to the ARM.
command to the ARM.
DAT BLK
Data block: The card sends a block of data to the ARM. The data content is preceded by a start bit and is
followed by two CRC byte and an end bit.
followed by two CRC byte and an end bit.
The MMC/SD controller contains a single 256-bit FIFO that is used for both reading data from the memory
card and writing data to the memory card (see
card and writing data to the memory card (see
). The FIFO is organized as 32 eight-bit entries.
The conversion from the 32-bit bus to the byte format of the FIFO follows the little-endian convention
(details are provided in later sections). The read and write FIFOs act as an interim location to store data
transferred from/to the card momentarily via the CPU or EDMA. The FIFO includes logic to generate
EDMA events and interrupts based on the amount of data in the FIFO and a programmable number of
bytes received/transmitted. Flags are set when the FIFO is full or empty.
(details are provided in later sections). The read and write FIFOs act as an interim location to store data
transferred from/to the card momentarily via the CPU or EDMA. The FIFO includes logic to generate
EDMA events and interrupts based on the amount of data in the FIFO and a programmable number of
bytes received/transmitted. Flags are set when the FIFO is full or empty.
SPRUE30B – September 2006
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
15