Delta Tau GEO BRICK LV Manuel D’Utilisation
Turbo PMAC User Manual
42
Talking to Turbo PMAC
Serial Controller Addressing
A controller is addressed with the @n command, where n is a hex digit from 0 to F. When the @n
command is sent over the serial cable, the controller whose value of I0 is equal to n becomes the
addressed controller; all others become unaddressed. Only the addressed controller will respond to
commands and acknowledge them, driving its output data and handshake lines (which are tri-stated on the
unaddressed controllers to prevent signal contention).
A controller is addressed with the @n command, where n is a hex digit from 0 to F. When the @n
command is sent over the serial cable, the controller whose value of I0 is equal to n becomes the
addressed controller; all others become unaddressed. Only the addressed controller will respond to
commands and acknowledge them, driving its output data and handshake lines (which are tri-stated on the
unaddressed controllers to prevent signal contention).
If the @@ command is sent over the serial cable, all controllers on the cable will respond to action
commands. Commands requiring a data response are not permitted in this mode. The Turbo PMAC
whose I0 value is 0 will drive its output data and handshake lines (all others tri-state theirs) and
acknowledge host commands.
commands. Commands requiring a data response are not permitted in this mode. The Turbo PMAC
whose I0 value is 0 will drive its output data and handshake lines (all others tri-state theirs) and
acknowledge host commands.
Optional Clock Sharing
It is possible to share servo and phase clock signals over additional lines on the RS-422 multi-drop cable.
This can prevent long-term drift in continuous motion between controllers due to tolerances in the clock-
crystal frequency of each. Jumpers on each Turbo PMAC determine whether the controller will generate
its own servo and phase clock signals and output them on its serial port, or whether it will expect them as
inputs from its serial port. Only one controller on a multi-drop cable can be outputting its servo and
phase clocks. Only the frequency-control variables or jumpers on this controller affect the frequency of
the servo and phase clocks for all controllers on the cable.
It is possible to share servo and phase clock signals over additional lines on the RS-422 multi-drop cable.
This can prevent long-term drift in continuous motion between controllers due to tolerances in the clock-
crystal frequency of each. Jumpers on each Turbo PMAC determine whether the controller will generate
its own servo and phase clock signals and output them on its serial port, or whether it will expect them as
inputs from its serial port. Only one controller on a multi-drop cable can be outputting its servo and
phase clocks. Only the frequency-control variables or jumpers on this controller affect the frequency of
the servo and phase clocks for all controllers on the cable.
If the servo and phase clock signals are not being shared between controllers, these signals should not be
connected between controllers through the cable.
connected between controllers through the cable.
Bus Communications Port
Each configuration of Turbo PMAC has a bus port that provides faster communications than the serial
port. There are both the traditional backplane buses (ISA, PCI, VME) and the newer wire buses (USB,
Ethernet).
port. There are both the traditional backplane buses (ISA, PCI, VME) and the newer wire buses (USB,
Ethernet).
Most of these bus ports use the host port on the Turbo PMAC’s CPU (the VME bus uses a set of mailbox
registers instead). Many of them can also use optional dual-ported RAM (DPRAM) as an alternate path
to communicate with the CPU, although this communications uses the same physical path between the
host computer and the Turbo PMAC.
registers instead). Many of them can also use optional dual-ported RAM (DPRAM) as an alternate path
to communicate with the CPU, although this communications uses the same physical path between the
host computer and the Turbo PMAC.
It is possible to download new operational firmware through a bus communications port that uses the host
port on the Turbo PMAC’s CPU (see Resetting Turbo PMAC). This excludes the VME bus and any wire
bus interfaces that are using DPRAM communications only.
port on the Turbo PMAC’s CPU (see Resetting Turbo PMAC). This excludes the VME bus and any wire
bus interfaces that are using DPRAM communications only.
Backplane Buses
Several types of backplane buses are supported in various Turbo PMAC configurations. These buses
provide the highest-speed and lowest-latency communications, due to their high raw data rates (compared
to simple serial interfaces) and absence of intermediate processors (compared to the wire buses).
provide the highest-speed and lowest-latency communications, due to their high raw data rates (compared
to simple serial interfaces) and absence of intermediate processors (compared to the wire buses).
ISA (and PC/104) Bus
The ISA bus interface comes standard on board-level Turbo PMAC controllers with the –PC suffix (e.g.
Turbo PMAC-PC, Turbo PMAC2-PC). The PC/104 bus interface, a stack version of the ISA bus
(equivalent electrically and in software), comes standard on the 3U-format UMAC Turbo CPU board
(formerly Option 2 for this board, now always included).
The ISA bus interface comes standard on board-level Turbo PMAC controllers with the –PC suffix (e.g.
Turbo PMAC-PC, Turbo PMAC2-PC). The PC/104 bus interface, a stack version of the ISA bus
(equivalent electrically and in software), comes standard on the 3U-format UMAC Turbo CPU board
(formerly Option 2 for this board, now always included).
The basic communications on the ISA bus goes through the host port on the Turbo PMAC’s CPU. Dual-
ported RAM is an optional addition to this bus interface (see below). The address of the host port
communications in the I/O space of the ISA bus is selected by a bank of jumpers or DIP switches on the
Turbo PMAC board. The factory default setting is for base I/O address 528 (210 hex), and the interface
occupies 16 consecutive addresses in the PC’s I/O space.
ported RAM is an optional addition to this bus interface (see below). The address of the host port
communications in the I/O space of the ISA bus is selected by a bank of jumpers or DIP switches on the
Turbo PMAC board. The factory default setting is for base I/O address 528 (210 hex), and the interface
occupies 16 consecutive addresses in the PC’s I/O space.