Manuels d'utilisation pour Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105

Atmel

Codes de produits

ATEVK1105

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Fiche De Données (ATEVK1105)

Table des matières

Fiche De Données (ATEVK1105)

Taille:

240 ko
Pages:

28
Language:

English

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Fiche De Données (ATEVK1105)

Table des matières

Features
1
1. Description
3
2. Configuration Summary
4
3. Abbreviations
4
4. Blockdiagram
5
- 4.1 Processor and architecture
  6
5. Signals Description
8
6. Power Considerations
13
- 6.1 Power Supplies
  13
- 6.2 Voltage Regulator
  14
  - 6.2.1 Single Power Supply
    14
  - 6.2.2 Dual Power Supply
    14
- 6.3 Analog-to-Digital Converter (A.D.C) reference.
  15
7. Package and Pinout
16
8. I/O Line Considerations
20
- 8.1 JTAG pins
  20
- 8.2 RESET_N pin
  20
- 8.3 TWI pins
  20
- 8.4 GPIO pins
  20
9. Processor and Architecture
21
- 9.1 AVR32 Architecture
  21
- 9.2 The AVR32UC CPU
  21
- 9.3 Programming Model
  25
- 9.4 Exceptions and Interrupts
  29
10. Memories
33
- 10.1 Embedded Memories
  33
- 10.2 Physical Memory Map
  33
- 10.3 Bus Matrix Connections
  34
11. Fuses Settings
36
- 11.1 Flash General Purpose Fuse Register (FGPFRLO)
  36
- 11.2 Default Fuse Value
  37
12. Peripherals
38
- 12.1 Peripheral address map
  38
- 12.2 CPU Local Bus Mapping
  39
- 12.3 Interrupt Request Signal Map
  41
- 12.4 Clock Connections
  43
  - 12.4.1 Timer/Counters
    43
  - 12.4.2 USARTs
    43
  - 12.4.3 SPIs
    44
- 12.5 Nexus OCD AUX port connections
  44
- 12.6 PDC handshake signals
  44
- 12.7 Peripheral Multiplexing on I/O lines
  45
- 12.8 Oscillator Pinout
  48
- 12.9 USART Configuration
  48
- 12.10 GPIO
  49
- 12.11 Peripheral overview
  49
13. Power Manager (PM)
53
- 13.1 Features
  53
- 13.2 Description
  53
- 13.3 Block Diagram
  54
- 13.4 Product Dependencies
  55
  - 13.4.1 I/O Lines
    55
  - 13.4.2 Interrupt
    55
  - 13.4.3 Clock implementation
    55
- 13.5 Functional Description
  55
- 13.6 User Interface
  66
14. Real Time Counter (RTC)
86
- 14.1 Features
  86
- 14.2 Description
  86
- 14.3 Block Diagram
  87
- 14.4 Product Dependencies
  87
  - 14.4.1 Power Management
    87
  - 14.4.2 Interrupt
    87
  - 14.4.3 Debug Operation
    87
  - 14.4.4 Clocks
    87
- 14.5 Functional Description
  87
  - 14.5.1 RTC operation
    87
    - 14.5.1.1 Source clock
      87
    - 14.5.1.2 Counter operation
      88
    - 14.5.1.3 RTC Interrupt
      88
    - 14.5.1.4 RTC wakeup
      88
    - 14.5.1.5 Busy bit
      88
- 14.6 User Interface
  89
15. Watchdog Timer (WDT)
94
- 15.1 Features
  94
- 15.2 Description
  94
- 15.3 Block Diagram
  94
- 15.4 Product Dependencies
  94
  - 15.4.1 Power Management
    94
  - 15.4.2 Debug Operation
    94
  - 15.4.3 Clocks
    94
- 15.5 Functional Description
  95
- 15.6 User Interface
  96
  - 15.6.1 WDT Control
    97
  - 15.6.2 WDT Clear
    98
16. Interrupt Controller (INTC)
99
- 16.1 Description
  99
- 16.2 Block Diagram
  99
- 16.3 Operation
  99
- 16.4 User Interface
  101
17. External Interrupts Controller (EIC)
105
- 17.1 Features
  105
- 17.2 Description
  105
- 17.3 Block Diagram
  106
- 17.4 Product Dependencies
  106
  - 17.4.1 I/O Lines
    106
  - 17.4.2 Power Management
    106
  - 17.4.3 Interrupt
    106
- 17.5 Functional Description
  107
- 17.6 User Interface
  109
18. Flash Controller (FLASHC)
115
- 18.1 Features
  115
- 18.2 Description
  115
- 18.3 Product dependencies
  115
  - 18.3.1 Power management
    115
  - 18.3.2 Interrupt
    115
- 18.4 Functional description
  116
- 18.5 Flash commands
  118
- 18.6 General-purpose fuse bits
  120
- 18.7 Security bit
  122
- 18.8 User interface
  123
19. HSB Bus Matrix (HMATRIX)
132
- 19.1 Features
  132
- 19.2 Description
  132
- 19.3 Memory Mapping
  132
- 19.4 Special Bus Granting Mechanism
  132
  - 19.4.1 No Default Master
    133
  - 19.4.2 Last Access Master
    133
  - 19.4.3 Fixed Default Master
    133
- 19.5 Arbitration
  133
- 19.6 Slave and Master assignation
  135
- 19.7 User Interface
  136
20. External Bus Interface (EBI)
145
- 20.1 Features
  145
- 20.2 Description
  145
- 20.3 Block Diagram
  146
  - 20.3.1 External Bus Interface
    146
- 20.4 I/O Lines Description
  147
- 20.5 Application Example
  148
  - 20.5.1 Hardware Interface
    148
  - 20.5.2 Connection Examples
    150
- 20.6 Product Dependencies
  151
  - 20.6.1 I/O Lines
    151
  - 20.6.2 Power Management
    151
  - 20.6.3 Interrupt
    151
- 20.7 Functional Description
  151
  - 20.7.1 Bus Multiplexing
    151
  - 20.7.2 Pull-up Control
    151
  - 20.7.3 Static Memory Controller
    152
  - 20.7.4 SDRAM Controller
    152
21. Peripheral DMA Controller (PDCA)
153
- 21.1 Features
  153
- 21.2 Overview
  153
- 21.3 Block Diagram
  154
- 21.4 Functional Description
  154
  - 21.4.1 Configuration
    154
  - 21.4.2 Memory Pointer
    154
  - 21.4.3 Transfer Counter
    155
  - 21.4.4 Reload Registers
    155
  - 21.4.5 Peripheral Selection
    155
  - 21.4.6 Transfer Size
    155
  - 21.4.7 Enabling and Disabling
    155
  - 21.4.8 Interrupts
    155
  - 21.4.9 Priority
    156
  - 21.4.10 Error Handling
    156
- 21.5 User Interface
  156
22. General-Purpose Input/Output Controller (GPIO)
170
- 22.1 Features
  170
- 22.2 Overview
  170
- 22.3 Product dependencies
  170
- 22.4 Functional Description
  171
  - 22.4.1 Pull-up Resistor Control
    171
  - 22.4.2 I/O Line or Peripheral Function Selection
    172
  - 22.4.3 Peripheral Selection
    172
  - 22.4.4 Output Control
    172
  - 22.4.5 Open Drain Mode
    172
  - 22.4.6 Inputs
    172
  - 22.4.7 Interrupts
    173
  - 22.4.8 Input Glitch Filter
    173
  - 22.4.9 Interrupt Timings
    173
- 22.5 General Purpose Input/Output (GPIO) User Interface
  175
- 22.6 Programming Examples
  189
  - 22.6.1 8-bit LED-Chaser
    189
  - 22.6.2 Configuration of USART pins
    189
23. Serial Peripheral Interface (SPI)
191
- 23.1 Features
  191
- 23.2 Description
  191
- 23.3 Block Diagram
  192
- 23.4 Application Block Diagram
  193
- 23.5 Signal Description
  194
- 23.6 Product Dependencies
  195
  - 23.6.1 I/O Lines
    195
  - 23.6.2 Power Management
    195
  - 23.6.3 Interrupt
    195
- 23.7 Functional Description
  196
- 23.8 Serial Peripheral Interface (SPI) User Interface
  206
24. Two-Wire Interface (TWI)
220
- 24.1 Features
  220
- 24.2 Overview
  220
- 24.3 List of Abbreviations
  221
- 24.4 Block Diagram
  221
- 24.5 Application Block Diagram
  222
- 24.6 I/O Lines Description
  222
- 24.7 Product Dependencies
  222
  - 24.7.1 I/O Lines
    222
  - 24.7.2 Power Management
    222
  - 24.7.3 Interrupt
    223
- 24.8 Functional Description
  223
  - 24.8.1 Transfer Format
    223
- 24.9 Modes of Operation
  223
- 24.10 Master Mode
  224
- 24.11 Internal Address Usage Using the Peripheral DMA Controller (PDC)
  228
- 24.12 Multi-master Mode
  235
  - 24.12.1 Definition
    235
  - 24.12.2 Different Multi-master Modes
    235
    - 24.12.2.1 TWI as Master Only
      235
    - 24.12.2.2 TWI as Master or Slave
      235
- 24.13 Slave Mode
  238
- 24.14 Two-wire Interface (TWI) User Interface
  246
25. Synchronous Serial Controller (SSC)
259
- 25.1 Features
  259
- 25.2 Overview
  259
- 25.3 Block Diagram
  260
- 25.4 Application Block Diagram
  260
- 25.5 I/O Lines Description
  261
- 25.6 Product Dependencies
  261
  - 25.6.1 I/O Lines
    261
  - 25.6.2 Power Management
    261
  - 25.6.3 Interrupt
    261
- 25.7 Functional Description
  261
  - 25.7.1 Clock Management
    262
  - 25.7.2 Transmitter Operations
    265
  - 25.7.3 Receiver Operations
    266
  - 25.7.4 Start
    267
  - 25.7.5 Frame Sync
    269
    - 25.7.5.1 Frame Sync Data
      269
    - 25.7.5.2 Frame Sync Edge Detection
      269
  - 25.7.6 Receive Compare Modes
    270
    - 25.7.6.1 Compare Functions
      270
  - 25.7.7 Data Format
    270
  - 25.7.8 Loop Mode
    272
  - 25.7.9 Interrupt
    272
- 25.8 SSC Application Examples
  273
- 25.9 User Interface
  275
26. Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
299
- 26.1 Features
  299
- 26.2 Overview
  299
- 26.3 Block Diagram
  300
- 26.4 Application Block Diagram
  301
- 26.5 I/O Lines Description
  302
- 26.6 Product Dependencies
  303
  - 26.6.1 I/O Lines
    303
  - 26.6.2 Power Manager (PM)
    303
  - 26.6.3 Interrupt
    303
- 26.7 Functional Description
  304
- 26.8 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) User Interface
  339
27. Static Memory Controller (SMC)
366
- 27.1 Features
  366
- 27.2 Overview
  366
- 27.3 Block Diagram
  367
- 27.4 I/O Lines Description
  367
- 27.5 Product Dependencies
  368
  - 27.5.1 EBI I/O Lines
    368
- 27.6 Functionnal Description
  368
- 27.7 User Interface
  403
  - 27.7.1 Setup Register
    404
  - 27.7.2 Pulse Register
    405
  - 27.7.3 Cycle Register
    406
  - 27.7.4 MODE Register
    407
28. SDRAM Controller (SDRAMC)
410
- 28.1 Features
  410
- 28.2 Description
  410
- 28.3 Block Diagram
  411
- 28.4 I/O Lines Description
  411
- 28.5 Application Example
  412
  - 28.5.1 Hardware Interface
    412
  - 28.5.2 Software Interface
    413
    - 28.5.2.1 32-bit Memory Data Bus Width
      413
    - 28.5.2.2 16-bit Memory Data Bus Width
      414
- 28.6 Product Dependencies
  415
  - 28.6.1 SDRAM Device Initialization
    415
  - 28.6.2 I/O Lines
    416
  - 28.6.3 Interrupt
    416
- 28.7 Functional Description
  417
- 28.8 SDRAM Controller User Interface
  424
29. Ethernet MAC (MACB)
437
- 29.1 Features
  437
- 29.2 Description
  437
- 29.3 Block Diagram
  438
- 29.4 Product Dependencies
  438
  - 29.4.1 I/O Lines
    438
  - 29.4.2 Power Management
    438
  - 29.4.3 Interrupt
    439
- 29.5 Functional Description
  439
  - 29.5.1 Memory Interface
    439
    - 29.5.1.1 FIFO
      439
    - 29.5.1.2 Receive Buffers
      440
    - 29.5.1.3 Transmit Buffer
      442
  - 29.5.2 Transmit Block
    444
  - 29.5.3 Pause Frame Support
    444
  - 29.5.4 Receive Block
    446
  - 29.5.5 Address Checking Block
    446
  - 29.5.6 Broadcast Address
    447
  - 29.5.7 Hash Addressing
    447
  - 29.5.8 External Address Matching
    448
  - 29.5.9 Copy All Frames (or Promiscuous Mode)
    448
  - 29.5.10 Type ID Checking
    448
  - 29.5.11 VLAN Support
    449
  - 29.5.12 PHY Maintenance
    449
  - 29.5.13 Media Independent Interface
    449
    - 29.5.13.1 RMII Transmit and Receive Operation
      450
- 29.6 Programming Interface
  451
  - 29.6.1 Initialization
    451
    - 29.6.1.1 Configuration
      451
    - 29.6.1.2 Receive Buffer List
      451
    - 29.6.1.3 Transmit Buffer List
      452
    - 29.6.1.4 Address Matching
      452
    - 29.6.1.5 Interrupts
      452
    - 29.6.1.6 Transmitting Frames
      452
    - 29.6.1.7 Receiving Frames
      453
- 29.7 Ethernet MAC (MACB) User Interface
  454
30. USB On-The-Go Interface (USBB)
497
- 30.1 Features
  497
- 30.2 Description
  497
- 30.3 Block Diagram
  499
- 30.4 Application Block Diagram
  500
  - 30.4.1 Device Mode
    500
    - 30.4.1.1 Bus-Powered Device
      500
    - 30.4.1.2 Self-Powered Device
      500
  - 30.4.2 Host and OTG Modes
    501
- 30.5 I/O Lines Description
  501
- 30.6 Product Dependencies
  502
  - 30.6.1 I/O Lines
    502
  - 30.6.2 Power Management
    502
  - 30.6.3 Interrupts
    502
- 30.7 Functional Description
  503
  - 30.7.1 USB General Operation
    503
    - 30.7.1.1 Introduction
      503
    - 30.7.1.2 Power-On and Reset
      503
    - 30.7.1.3 Interrupts
      504
    - 30.7.1.4 MCU Power Modes
      505
    - 30.7.1.5 Speed Control
      506
    - 30.7.1.6 DPRAM Management
      506
    - 30.7.1.7 Pad Suspend
      508
    - 30.7.1.8 Customizing of OTG Timers
      509
    - 30.7.1.9 Plug-In Detection
      509
    - 30.7.1.10 ID Detection
      510
  - 30.7.2 USB Device Operation
    511
    - 30.7.2.1 Introduction
      511
    - 30.7.2.2 Power-On and Reset
      511
    - 30.7.2.3 USB Reset
      511
    - 30.7.2.4 Endpoint Reset
      512
    - 30.7.2.5 Endpoint Activation
      512
    - 30.7.2.6 Address Setup
      513
    - 30.7.2.7 Suspend and Wake-Up
      513
    - 30.7.2.8 Detach
      513
    - 30.7.2.9 Remote Wake-Up
      513
    - 30.7.2.10 STALL Request
      514
    - 30.7.2.11 Management of Control Endpoints
      514
    - 30.7.2.12 Management of IN Endpoints
      516
    - 30.7.2.13 Management of OUT Endpoints
      518
    - 30.7.2.14 Underflow
      519
    - 30.7.2.15 Overflow
      520
    - 30.7.2.16 CRC Error
      520
    - 30.7.2.17 Interrupts
      520
  - 30.7.3 USB Host Operation
    522
    - 30.7.3.1 Description of Pipes
      522
    - 30.7.3.2 Power-On and Reset
      522
    - 30.7.3.3 Device Detection
      523
    - 30.7.3.4 USB Reset
      523
    - 30.7.3.5 Pipe Reset
      523
    - 30.7.3.6 Pipe Activation
      523
    - 30.7.3.7 Address Setup
      524
    - 30.7.3.8 Remote Wake-Up
      524
    - 30.7.3.9 Management of Control Pipes
      525
    - 30.7.3.10 Management of IN Pipes
      525
    - 30.7.3.11 Management of OUT Pipes
      526
    - 30.7.3.12 CRC Error
      527
    - 30.7.3.13 Interrupts
      528
  - 30.7.4 USB DMA Operation
    529
- 30.8 USB User Interface
  530
31. Timer/Counter (TC)
639
- 31.1 Features
  639
- 31.2 Description
  639
- 31.3 Block Diagram
  640
- 31.4 Pin Name List
  641
- 31.5 Product Dependencies
  641
  - 31.5.1 I/O Lines
    641
  - 31.5.2 Debug operation
    641
  - 31.5.3 Power Management
    641
  - 31.5.4 Interrupt
    641
- 31.6 Functional Description
  641
  - 31.6.1 TC Description
    641
    - 31.6.1.1 16-bit Counter
      641
    - 31.6.1.2 Clock Selection
      641
    - 31.6.1.3 Clock Control
      642
    - 31.6.1.4 TC Operating Modes
      643
    - 31.6.1.5 Trigger
      643
  - 31.6.2 Capture Operating Mode
    644
    - 31.6.2.1 Capture Registers A and B
      644
    - 31.6.2.2 Trigger Conditions
      644
  - 31.6.3 Waveform Operating Mode
    646
    - 31.6.3.1 Waveform Selection
      646
    - 31.6.3.2 WAVSEL = 00
      648
    - 31.6.3.3 WAVSEL = 10
      649
    - 31.6.3.4 WAVSEL = 01
      650
    - 31.6.3.5 WAVSEL = 11
      651
    - 31.6.3.6 External Event/Trigger Conditions
      652
    - 31.6.3.7 Output Controller
      653
- 31.7 Timer Counter (TC) User Interface
  654
32. Pulse Width Modulation Controller (PWM)
673
- 32.1 Features
  673
- 32.2 Description
  673
- 32.3 Block Diagram
  674
- 32.4 I/O Lines Description
  674
- 32.5 Product Dependencies
  675
  - 32.5.1 I/O Lines
    675
  - 32.5.2 Debug operation
    675
  - 32.5.3 Power Management
    675
  - 32.5.4 Interrupt Sources
    675
- 32.6 Functional Description
  676
- 32.7 Pulse Width Modulation (PWM) Controller User Interface
  684
33. Analog-to-Digital Converter (ADC)
699
- 33.1 Features
  699
- 33.2 Overview
  699
- 33.3 Block Diagram
  700
- 33.4 I/O Lines Description
  700
- 33.5 Product Dependencies
  700
  - 33.5.1 GPIO
    700
  - 33.5.2 Analog Inputs
    701
  - 33.5.3 Power Manager
    701
  - 33.5.4 Interrupt Controller
    701
  - 33.5.5 Timer Triggers
    701
  - 33.5.6 Conversion Performances
    701
- 33.6 Functional Description
  702
- 33.7 User Interface
  707
34. Audio Bitstream DAC (ABDAC)
721
- 34.1 Features
  721
- 34.2 Description
  721
- 34.3 Block Diagram
  722
- 34.4 Pin Name List
  722
- 34.5 Product Dependencies
  722
  - 34.5.1 I/O Lines
    722
  - 34.5.2 Power Management
    722
  - 34.5.3 Clock Management
    723
  - 34.5.4 Interrupts
    723
  - 34.5.5 DMA
    723
- 34.6 Functional Description
  723
  - 34.6.1 Equalization Filter
    723
  - 34.6.2 Interpolation filter
    724
  - 34.6.3 Sigma Delta Modulator
    724
  - 34.6.4 Data Format
    724
- 34.7 Audio Bitstream DAC User Interface
  725
- 34.8 Frequency Response
  733
35. On-Chip Debug
734
- 35.1 Features
  734
- 35.2 Overview
  734
- 35.3 Block diagram
  735
- 35.4 Functional description
  735
  - 35.4.1 JTAG-based debug features
    735
    - 35.4.1.1 Debug Communication Channel
      736
    - 35.4.1.2 Breakpoints
      736
    - 35.4.1.3 OCD Mode
      737
    - 35.4.1.4 Monitor Mode
      737
    - 35.4.1.5 Program Counter monitoring
      737
  - 35.4.2 Memory Service Unit
    737
    - 35.4.2.1 Cyclic Redundancy Check (CRC)
      737
    - 35.4.2.2 NanoTrace
      737
  - 35.4.3 AUX-based debug features
    737
36. JTAG and Boundary Scan
741
- 36.1 Features
  741
- 36.2 Overview
  741
- 36.3 Block diagram
  742
- 36.4 I/O Lines Description
  743
- 36.5 Product Dependencies
  743
  - 36.5.1 I/O Lines
    743
- 36.6 Functional description
  743
  - 36.6.1 JTAG interface
    743
  - 36.6.2 Typical sequence
    744
    - 36.6.2.1 Scanning in JTAG instruction
      744
    - 36.6.2.2 Scanning in/out data
      745
  - 36.6.3 Boundary-Scan
    745
  - 36.6.4 Service Access Bus
    746
    - 36.6.4.1 Busy reporting
      746
    - 36.6.4.2 Error reporting
      747
  - 36.6.5 Memory programming
    747
- 36.7 JTAG Instruction Summary
  748
  - 36.7.1 Security restrictions
    748
- 36.8 Public JTAG instructions
  749
  - 36.8.1 IDCODE
    749
  - 36.8.2 SAMPLE_PRELOAD
    749
  - 36.8.3 EXTEST
    749
  - 36.8.4 INTEST
    749
  - 36.8.5 CLAMP
    750
  - 36.8.6 BYPASS
    750
- 36.9 Private JTAG Instructions
  750
  - 36.9.1 Notation
    750
  - 36.9.2 NEXUS_ACCESS
    751
  - 36.9.3 MEMORY_SERVICE
    752
  - 36.9.4 MEMORY_SIZED_ACCESS
    753
  - 36.9.5 MEMORY_WORD_ACCESS
    754
  - 36.9.6 MEMORY_BLOCK_ACCESS
    755
  - 36.9.7 CANCEL_ACCESS
    756
  - 36.9.8 SYNC
    757
  - 36.9.9 AVR_RESET
    757
  - 36.9.10 CHIP_ERASE
    757
  - 36.9.11 HALT
    758
- 36.10 JTAG Data Registers
  760
- 36.11 SAB address map
  761
37. Boot Sequence
762
- 37.1 Starting of clocks
  762
- 37.2 Fetching of initial instructions
  762
38. Electrical Characteristics
763
- 38.1 Absolute Maximum Ratings*
  763
- 38.2 DC Characteristics
  764
- 38.3 Regulator characteristics
  765
- 38.4 Analog characteristics
  765
  - 38.4.1 BOD
    765
  - 38.4.2 POR
    766
- 38.5 Power Consumption
  767
- 38.6 Clock Characteristics
  769
- 38.7 Crystal Oscillator Characteristis
  770
- 38.8 ADC Characteristics
  772
- 38.9 EBI Timings
  774
  - 38.9.1 SDRAM Signals
    777
- 38.10 JTAG Timings
  780
  - 38.10.1 JTAG Interface Signals
    780
- 38.11 SPI Characteristics
  781
- 38.12 MACB Characteristics
  783
- 38.13 Flash Characteristics
  785
39. Mechanical Characteristics
787
- 39.1 Thermal Considerations
  787
  - 39.1.1 Thermal Data
    787
  - 39.1.2 Junction Temperature
    787
- 39.2 Package Drawings
  788
- 39.3 Soldering Profile
  791
40. Ordering Information
792
- 40.1 Automotive Quality Grade
  792
41. Errata
793
- 41.1 Rev. K
  793
  - 41.1.1 PWM
    793
  - 41.1.2 ADC
    793
  - 41.1.3 SPI
    793
  - 41.1.4 Power Manager
    794
  - 41.1.5 PDCA
    794
  - 41.1.6 TWI
    794
  - 41.1.7 USART
    794
  - 41.1.8 Processor and Architecture
    794
- 41.2 Rev. J
  796
  - 41.2.1 PWM
    796
  - 41.2.2 ADC
    796
  - 41.2.3 SPI
    796
  - 41.2.4 Power Manager
    797
  - 41.2.5 PDCA
    797
  - 41.2.6 TWI
    797
  - 41.2.7 SDRAMC
    797
  - 41.2.8 GPIO
    797
  - 41.2.9 USART
    798
  - 41.2.10 Processor and Architecture
    798
- 41.3 Rev. I
  799
  - 41.3.1 PWM
    799
  - 41.3.2 ADC
    799
  - 41.3.3 SPI
    799
  - 41.3.4 Power Manager
    800
  - 41.3.5 Flashc
    800
  - 41.3.6 PDCA
    800
  - 41.3.7 GPIO
    801
  - 41.3.8 USART
    801
  - 41.3.9 TWI
    801
  - 41.3.10 SDRAMC
    801
  - 41.3.11 Processor and Architecture
    801
- 41.4 Rev. H
  803
  - 41.4.1 PWM
    803
  - 41.4.2 ADC
    803
  - 41.4.3 SPI
    803
  - 41.4.4 Power Manager
    804
  - 41.4.5 FLASHC
    804
  - 41.4.6 PDCA
    805
  - 41.4.7 TWI
    805
  - 41.4.8 SDRAMC
    805
  - 41.4.9 GPIO
    805
  - 41.4.10 USART
    805
  - 41.4.11 Processor and Architecture
    805
- 41.5 Rev. E
  807
  - 41.5.1 SPI
    807
  - 41.5.2 PWM
    808
  - 41.5.3 SSC
    808
  - 41.5.4 USB
    809
  - 41.5.5 Processor and Architecture
    809
  - 41.5.6 SDRAMC
    811
  - 41.5.7 USART
    811
  - 41.5.8 Power Manager
    812
  - 41.5.9 HMatrix
    813
  - 41.5.10 ADC
    813
  - 41.5.11 ABDAC
    814
  - 41.5.12 FLASHC
    814
  - 41.5.13 RTC
    814
  - 41.5.14 OCD
    815
  - 41.5.15 PDCA
    815
  - 41.5.16 TWI
    815
42. Datasheet Revision History
816
- 42.1 Rev. H – 03/09
  816
- 42.2 Rev. G – 01/09
  816
- 42.3 Rev. F – 08/08
  816
- 42.4 Rev. E – 04/08
  816
- 42.5 Rev. D – 04/08
  816
- 42.6 Rev. C – 10/07
  817
- 42.7 Rev. B – 10/07
  817
- 42.8 Rev. A – 03/07
  817
Table of Contents
818

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English

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Fiche De Données (ATEVK1105)

Fiche De Données (ATEVK1105)

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81 ko
Pages:

2

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