Manuels d'utilisation pour Fujitsu MHE2064AT

Table des matières

• Front title

  1
• Preface

  6
• Contents

  14
• Illustrations

  19
• CHAPTER 1 Device Overview

  22
  • 1.1 Features

    23
    • 1.1.1 Functions and performance

      23
    • 1.1.2 Adaptability

      23
    • 1.1.3 Interface

      24
  • 1.2 Device Specifications

    25
    • 1.2.1 Specifications summary

      25
    • 1.2.2 Model and product number

      27
  • 1.3 Power Requirements

    27
  • 1.4 Environmental Specifications

    29
  • 1.5 Acoustic Noise

    30
  • 1.6 Shock and Vibration

    30
  • 1.7 Reliability

    31
  • 1.8 Error Rate

    32
  • 1.9 Media Defects

    32
• CHAPTER 2 Device Configuration

  34
  • 2.1 Device Configuration

    35
  • 2.2 System Configuration

    37
    • 2.2.1 ATA interface

      37
    • 2.2.2 1 drive connection

      37
    • 2.2.3 2 drives connection

      37
• CHAPTER 3 Installation Conditions

  40
  • 3.1 Dimensions

    41
  • 3.2 Mounting

    43
  • 3.3 Cable Connections

    47
    • 3.3.1 Device connector

      47
    • 3.3.2 Cable connector specifications

      48
    • 3.3.3 Device connection

      48
    • 3.3.4 Power supply connector (CN1)

      49
  • 3.4 Jumper Settings

    49
    • 3.4.1 Location of setting jumpers

      49
    • 3.4.2 Factory default setting

      50
    • 3.4.3 Master drive-slave drive setting

      50
    • 3.4.4 CSEL setting

      51
• CHAPTER 4 Theory of Device Operation

  54
  • 4.1 Outline

    55
  • 4.2 Subassemblies

    55
    • 4.2.1 Disk

      55
    • 4.2.2 Head

      55
    • 4.2.3 Spindle

      56
    • 4.2.4 Actuator

      56
    • 4.2.5 Air filter

      56
  • 4.3 Circuit Configuration

    57
  • 4.4 Power-on Sequence

    59
  • 4.5 Self-calibration

    60
    • 4.5.1 Self-calibration contents

      60
    • 4.5.2 Execution timing of self-calibration

      61
    • 4.5.3 Command processing during self-calibration

      62
  • 4.6 Read/write Circuit

    62
    • 4.6.1 Read/write preamplifier (PreAMP)

      62
    • 4.6.2 Write circuit

      63
    • 4.6.3 Read circuit

      65
    • 4.6.4 Digital PLL circuit

      66
  • 4.7 Servo Control

    67
    • 4.7.1 Servo control circuit

      67
    • 4.7.2 Data-surface servo format

      71
    • 4.7.3 Servo frame format

      71
    • 4.7.4 Actuator motor control

      72
    • 4.7.5 Spindle motor control

      73
• CHAPTER 5 Interface

  76
  • 5.1 Physical Interface

    77
    • 5.1.1 Interface signals

      77
    • 5.1.2 Signal assignment on the connector

      78
  • 5.2 Logical Interface

    81
    • 5.2.1 I/O registers

      82
    • 5.2.2 Command block registers

      83
    • 5.2.3 Control block registers

      88
  • 5.3 Host Commands

    88
    • 5.3.1 Command code and parameters

      89
    • 5.3.2 Command descriptions

      91
    • 5.3.3 Error posting

      146
  • 5.4 Command Protocol

    148
    • 5.4.1 Data transferring commands from device to host

      148
    • 5.4.2 Data transferring commands from host to device

      150
    • 5.4.3 Commands without data transfer

      152
    • 5.4.4 Other commands

      153
    • 5.4.5 DMA data transfer commands

      153
  • 5.5 Ultra DMA Feature Set

    155
    • 5.5.1 Overview

      155
    • 5.5.2 Phases of operation

      156
      • 5.5.2.1 Ultra DMA burst initiation phase

        156
      • 5.5.2.2 Data transfer phase

        157
      • 5.5.2.3 Ultra DMA burst termination phase

        157
    • 5.5.3 Ultra DMA data in commands

      158
      • 5.5.3.1 Initiating an Ultra DMA data in burst

        158
      • 5.5.3.2 The data in transfer

        159
      • 5.5.3.3 Pausing an Ultra DMA data in burst

        159
      • 5.5.3.4 Terminating an Ultra DMA data in burst

        160
    • 5.5.4 Ultra DMA data out commands

      163
      • 5.5.4.1 Initiating an Ultra DMA data out burst

        163
      • 5.5.4.2 The data out transfer

        163
      • 5.5.4.3 Pausing an Ultra DMA data out burst

        164
      • 5.5.4.4 Terminating an Ultra DMA data out burst

        165
    • 5.5.5 Ultra DMA CRC rules

      167
    • 5.5.6 Series termination required for Ultra DMA

      169
  • 5.6 Timing

    170
    • 5.6.1 PIO data transfer

      170
    • 5.6.2 Single word DMA data transfer

      172
    • 5.6.3 Multiword DMA data transfer

      173
    • 5.6.4 Transfer of Ultra DMA data

      174
      • 5.6.4.1 Starting of Ultra DMA data In Burst

        174
      • 5.6.4.2 Ultra DMA data burst timing requirements

        175
      • 5.6.4.3 Sustained Ultra DMA data in burst

        177
      • 5.6.4.4 Host pausing an Ultra DMA data in burst

        178
      • 5.6.4.5 Device terminating an Ultra DMA data in burst

        179
      • 5.6.4.6 Host terminating an Ultra DMA data in burst

        180
      • 5.6.4.7 Initiating an Ultra DMA data out burst

        181
      • 5.6.4.8 Sustained Ultra DMA data out burst

        182
      • 5.6.4.9 Device pausing an Ultra DMA data out burst

        183
      • 5.6.4.10 Host terminating an Ultra DMA data out burst

        184
      • 5.6.4.11 Device terminating an Ultra DMA data in burst

        185
    • 5.6.5 Power-on and reset

      186
• CHAPTER 6 Operations

  188
  • 6.1 Device Response to the Reset

    189
    • 6.1.1 Response to power-on

      189
    • 6.1.2 Response to hardware reset

      191
    • 6.1.3 Response to software reset

      192
    • 6.1.4 Response to diagnostic command

      193
  • 6.2 Address Translation

    194
    • 6.2.1 Default parameters

      194
    • 6.2.2 Logical address

      195
  • 6.3 Power Save

    196
    • 6.3.1 Power save mode

      196
    • 6.3.2 Power commands

      198
  • 6.4 Defect Management

    198
    • 6.4.1 Spare area

      199
    • 6.4.2 Alternating defective sectors

      199
  • 6.5 Read-Ahead Cache

    201
    • 6.5.1 Data buffer configuration

      201
    • 6.5.2 Caching operation

      201
    • 6.5.3 Usage of read segment

      203
      • 6.5.3.1 Mis-hit (no hit)

        203
      • 6.5.3.2 Sequential read

        204
      • 6.5.3.3 Full hit (hit all)

        207
      • 6.5.3.4 Partially hit

        208
  • 6.6 Write Cache

    209
• Glossary

  212
• Acronyms and Abbreviations

  216
• Index

  218
• Comment Form

  223
• spine

  224
• back

  225