Manuel D’UtilisationTable des matièresIA-32 Intel® Architecture Software Developer’s Manual1Disclaimer2CONTENTS FOR VOLUME 3A AND 3B3CHAPTER 1 About This Manual371.1 IA-32 Processors Covered in this Manual371.2 Overview of The SYSTEM PROGRAMMING GUIDE381.3 Notational Conventions401.3.1 Bit and Byte Order411.3.2 Reserved Bits and Software Compatibility411.3.3 Instruction Operands421.3.4 Hexadecimal and Binary Numbers431.3.5 Segmented Addressing431.3.6 Syntax for CPUID, CR, and MSR Values431.3.7 Exceptions441.4 Related Literature45CHAPTER 2 System Architecture Overview492.1 Overview of the System-Level Architecture502.1.1 Global and Local Descriptor Tables532.1.1.1 Global and Local Descriptor Tables in IA-32 Mode532.1.2 System Segments, Segment Descriptors, and Gates532.1.2.1 Gates in IA-32e Mode542.1.3 Task-State Segments and Task Gates542.1.3.1 Task-State Segments in IA-32e Mode552.1.4 Interrupt and Exception Handling552.1.4.1 Interrupt and Exception Handling IA-32e Mode552.1.5 Memory Management552.1.5.1 Memory Management in IA-32e Mode562.1.6 System Registers562.1.6.1 System Registers in IA-32e Mode572.1.7 Other System Resources582.2 Modes of Operation582.3 System Flags and Fields in the EFLAGS Register602.3.1 System Flags and Fields in IA-32e Mode622.4 Memory-Management Registers622.4.1 Global Descriptor Table Register (GDTR)632.4.2 Local Descriptor Table Register (LDTR)632.4.3 IDTR Interrupt Descriptor Table Register642.4.4 Task Register (TR)642.5 Control Registers642.5.1 CPUID Qualification of Control Register Flags722.6 System Instruction Summary722.6.1 Loading and Storing System Registers732.6.2 Verifying of Access Privileges742.6.3 Loading and Storing Debug Registers752.6.4 Invalidating Caches and TLBs752.6.5 Controlling the Processor752.6.6 Reading Performance-Monitoring and Time-Stamp Counters762.6.6.1 Reading Counters in 64-Bit Mode772.6.7 Reading and Writing Model-Specific Registers772.6.7.1 Reading and Writing Model-Specific Registers in 64-Bit Mode77CHAPTER 3 Protected-Mode Memory Management813.1 Memory Management Overview813.2 Using Segments833.2.1 Basic Flat Model833.2.2 Protected Flat Model833.2.3 Multi-Segment Model853.2.4 Segmentation in IA-32e Mode863.2.5 Paging and Segmentation863.3 Physical Address Space863.3.1 Physical Address Space for Processors with Intel® EM64T873.4 Logical and Linear Addresses873.4.1 Logical Address Translation in IA-32e Mode883.4.2 Segment Selectors883.4.3 Segment Registers893.4.4 Segment Loading Instructions in IA-32e Mode913.4.5 Segment Descriptors923.4.5.1 Code- and Data-Segment Descriptor Types953.5 System Descriptor Types973.5.1 Segment Descriptor Tables983.5.2 Segment Descriptor Tables in IA-32e Mode1003.6 Paging (Virtual Memory) Overview1003.6.1 Paging Options1013.6.2 Page Tables and Directories in the Absence of Intel EM64T1023.7 Page Translation using 32-Bit Physical Addressing1023.7.1 Linear Address Translation (4-KByte Pages)1033.7.2 Linear Address Translation (4-MByte Pages)1043.7.3 Mixing 4-KByte and 4-MByte Pages1053.7.4 Memory Aliasing1053.7.5 Base Address of the Page Directory1053.7.6 Page-Directory and Page-Table Entries1063.7.7 Not Present Page-Directory and Page-Table Entries1103.8 36-Bit Physical Addressing Using the PAE Paging Mechanism1103.8.1 Enhanced Legacy PAE Paging1113.8.2 Linear Address Translation With PAE Enabled (4-KByte Pages)1113.8.3 Linear Address Translation With PAE Enabled (2-MByte Pages)1123.8.4 Accessing the Full Extended Physical Address Space With the Extended Page-Table Structure1133.8.5 Page-Directory and Page-Table Entries With Extended Addressing Enabled1143.9 36-Bit Physical Addressing Using the PSE-36 Paging Mechanism1173.10 PAE-Enabled Paging in IA-32e Mode1193.10.1 IA-32e Mode Linear Address Translation (4-KByte Pages)1193.10.2 IA-32e Mode Linear Address Translation (2-MByte Pages)1203.10.3 Enhanced Paging Data Structures1213.10.3.1 Reserved Bit Checking1233.11 Mapping Segments to Pages1253.12 Translation Lookaside Buffers (TLBs)126CHAPTER 4 Protection1314.1 Enabling and Disabling Segment and Page Protection1314.2 Fields and Flags Used for Segment-Level and Page-Level Protection1324.2.1 Code Segment Descriptor in 64-bit Mode1344.3 Limit Checking1354.3.1 Limit Checking in 64-bit Mode1364.4 Type Checking1364.4.1 Null Segment Selector Checking1384.4.1.1 NULL Segment Checking in 64-bit Mode1384.5 Privilege Levels1384.6 Privilege Level Checking When Accessing Data Segments1414.6.1 Accessing Data in Code Segments1434.7 Privilege Level Checking When Loading the SS Register1434.8 Privilege Level Checking When Transferring Program Control Between Code Segments1434.8.1 Direct Calls or Jumps to Code Segments1444.8.1.1 Accessing Nonconforming Code Segments1454.8.1.2 Accessing Conforming Code Segments1464.8.2 Gate Descriptors1474.8.3 Call Gates1484.8.3.1 IA-32e Mode Call Gates1494.8.4 Accessing a Code Segment Through a Call Gate1504.8.5 Stack Switching1534.8.5.1 Stack Switching in 64-bit Mode1564.8.6 Returning from a Called Procedure1564.8.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions1584.8.7.1 SYSENTER and SYSEXIT Instructions in IA-32e Mode1594.8.8 Fast System Calls in 64-bit Mode1604.9 Privileged Instructions1624.10 Pointer Validation1624.10.1 Checking Access Rights (LAR Instruction)1634.10.2 Checking Read/Write Rights (VERR and VERW Instructions)1644.10.3 Checking That the Pointer Offset Is Within Limits (LSL Instruction)1644.10.4 Checking Caller Access Privileges (ARPL Instruction)1654.10.5 Checking Alignment1674.11 Page-Level Protection1674.11.1 Page-Protection Flags1684.11.2 Restricting Addressable Domain1684.11.3 Page Type1684.11.4 Combining Protection of Both Levels of Page Tables1694.11.5 Overrides to Page Protection1694.12 Combining Page and Segment Protection1694.13 Page-Level Protection and Execute-Disable Bit1704.13.1 Detecting and Enabling the Execute-Disable Bit Capability1714.13.2 Execute-Disable Bit Page Protection1714.13.3 Reserved Bit Checking1734.13.4 Exception Handling174CHAPTER 5 Interrupt and Exception Handling1775.1 Interrupt and Exception Overview1775.2 Exception and Interrupt Vectors1785.3 Sources of Interrupts1785.3.1 External Interrupts1785.3.2 Maskable Hardware Interrupts1805.3.3 Software-Generated Interrupts1805.4 Sources of Exceptions1815.4.1 Program-Error Exceptions1815.4.2 Software-Generated Exceptions1815.4.3 Machine-Check Exceptions1815.5 Exception Classifications1815.6 Program or Task Restart1825.7 NonMaskable Interrupt (NMI)1845.7.1 Handling Multiple NMIs1845.8 Enabling and Disabling Interrupts1845.8.1 Masking Maskable Hardware Interrupts1855.8.2 Masking Instruction Breakpoints1865.8.3 Masking Exceptions and Interrupts When Switching Stacks1865.9 Priority Among Simultaneous Exceptions and Interrupts1865.10 Interrupt Descriptor Table (IDT)1885.11 IDT Descriptors1895.12 Exception and Interrupt Handling1905.12.1 Exception- or Interrupt-Handler Procedures1915.12.1.1 Protection of Exception- and Interrupt-Handler Procedures1935.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure1945.12.2 Interrupt Tasks1955.13 Error Code1975.14 Exception and Interrupt Handling in 64-bit Mode1985.14.1 64-Bit Mode IDT1985.14.2 64-Bit Mode Stack Frame1995.14.3 IRET in IA-32e Mode2005.14.4 Stack Switching in IA-32e Mode2005.14.5 Interrupt Stack Table2015.15 Exception and Interrupt Reference202Interrupt 0-Divide Error Exception (#DE)203Interrupt 1-Debug Exception (#DB)204Interrupt 2-NMI Interrupt205Interrupt 3-Breakpoint Exception (#BP)206Interrupt 4-Overflow Exception (#OF)207Interrupt 5-BOUND Range Exceeded Exception (#BR)208Interrupt 6-Invalid Opcode Exception (#UD)209Interrupt 7-Device Not Available Exception (#NM)211Interrupt 8-Double Fault Exception (#DF)213Interrupt 9-Coprocessor Segment Overrun215Interrupt 10-Invalid TSS Exception (#TS)216Interrupt 11-Segment Not Present (#NP)219Interrupt 12-Stack Fault Exception (#SS)221Interrupt 13-General Protection Exception (#GP)223Interrupt 14-Page-Fault Exception (#PF)227Interrupt 16-x87 FPU Floating-Point Error (#MF)231Interrupt 17-Alignment Check Exception (#AC)233Interrupt 18-Machine-Check Exception (#MC)235Interrupt 19-SIMD Floating-Point Exception (#XF)237Interrupts 32 to 255-User Defined Interrupts240CHAPTER 6 Task Management2436.1 Task Management Overview2436.1.1 Task Structure2436.1.2 Task State2446.1.3 Executing a Task2456.2 Task Management Data Structures2466.2.1 Task-State Segment (TSS)2466.2.2 TSS Descriptor2496.2.3 TSS Descriptor in 64-bit mode2506.2.4 Task Register2516.2.5 Task-Gate Descriptor2536.3 Task Switching2546.4 Task Linking2586.4.1 Use of Busy Flag To Prevent Recursive Task Switching2606.4.2 Modifying Task Linkages2606.5 Task Address Space2616.5.1 Mapping Tasks to the Linear and Physical Address Spaces2616.5.2 Task Logical Address Space2626.6 16-Bit Task-State Segment (TSS)2636.7 Task Management in 64-bit Mode265CHAPTER 7 Multiple-Processor Management2697.1 Locked Atomic Operations2707.1.1 Guaranteed Atomic Operations2717.1.2 Bus Locking2717.1.2.1 Automatic Locking2727.1.2.2 Software Controlled Bus Locking2737.1.3 Handling Self- and Cross-Modifying Code2747.1.4 Effects of a LOCK Operation on Internal Processor Caches2757.2 Memory Ordering2757.2.1 Memory Ordering in the Intel® Pentium® and Intel486™ Processors2767.2.2 Memory Ordering Pentium 4, Intel® Xeon®, and P6 Family Processors2767.2.3 Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors2787.2.4 Strengthening or Weakening the Memory Ordering Model2797.3 Propagation of Page Table and Page Directory Entry Changes to Multiple Processors2817.4 Serializing Instructions2827.5 Multiple-Processor (MP) Initialization2837.5.1 BSP and AP Processors2847.5.2 MP Initialization Protocol Requirements and Restrictions for Intel Xeon Processors2847.5.3 MP Initialization Protocol Algorithm for Intel Xeon Processors2857.5.4 MP Initialization Example2867.5.4.1 Typical BSP Initialization Sequence2877.5.4.2 Typical AP Initialization Sequence2897.5.5 Identifying Logical Processors in an MP System2907.6 Hyper-Threading and Multi-Core Technology2917.7 Detecting Hardware Multi-Threading Support and Topology2927.7.1 Initializing IA-32 Processors Supporting Hyper-Threading Technology2927.7.2 Initializing Dual-Core IA-32 Processors2937.7.3 Executing Multiple Threads on an IA-32 Processor Supporting Hardware Multi-Threading2937.7.4 Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading2937.8 Intel® Hyper-Threading Technology Architecture2947.8.1 State of the Logical Processors2957.8.2 APIC Functionality2967.8.3 Memory Type Range Registers (MTRR)2967.8.4 Page Attribute Table (PAT)2977.8.5 Machine Check Architecture2977.8.6 Debug Registers and Extensions2977.8.7 Performance Monitoring Counters2977.8.8 IA32_MISC_ENABLE MSR2987.8.9 Memory Ordering2987.8.10 Serializing Instructions2987.8.11 MICROCODE UPDATE Resources2987.8.12 Self Modifying Code2997.8.13 Implementation-Specific HT Technology Facilities2997.8.13.1 Processor Caches2997.8.13.2 Processor Translation Lookaside Buffers (TLBs)2997.8.13.3 Thermal Monitor3007.8.13.4 External Signal Compatibility3007.9 Dual-Core Architecture3017.9.1 Logical Processor Support3017.9.2 Memory Type Range Registers (MTRR)3027.9.3 Performance Monitoring Counters3027.9.4 IA32_MISC_ENABLE MSR3027.9.5 MICROCODE UPDATE Resources3027.10 Programming Considerations for Hardware Multi-Threading Capable Processors3037.10.1 Hierarchical Mapping of Shared Resources3037.10.2 Identifying Logical Processors in an MP System3047.10.3 Algorithm for Three-Level Mappings of APIC_ID3067.10.4 Identifying Topological Relationships in a MP System3097.11 Management of Idle and Blocked Conditions3137.11.1 HLT Instruction3137.11.2 PAUSE Instruction3147.11.3 Detecting Support MONITOR/MWAIT Instruction3147.11.4 MONITOR/MWAIT Instruction3157.11.5 Monitor/Mwait Address Range Determination3167.11.6 Required Operating System Support3177.11.6.1 Use the PAUSE Instruction in Spin-Wait Loops3177.11.6.2 Potential Usage of MONITOR/MWAIT in C0 Idle Loops3187.11.6.3 Halt Idle Logical Processors3197.11.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops3207.11.6.5 Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources3217.11.6.6 Eliminate Execution-Based Timing Loops3217.11.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory321CHAPTER 8 Advanced Programmable Interrupt Controller (APIC)3258.1 Local and I/O APIC Overview3258.2 System Bus Vs. APIC Bus3298.3 the Intel® 82489DX External APIC, The APIC, and the xAPIC3298.4 Local APIC3298.4.1 The Local APIC Block Diagram3308.4.2 Presence of the Local APIC3338.4.3 Enabling or Disabling the Local APIC3348.4.4 Local APIC Status and Location3358.4.5 Relocating the Local APIC Registers3358.4.6 Local APIC ID3368.4.7 Local APIC State3368.4.7.1 Local APIC State After Power-Up or Reset3378.4.7.2 Local APIC State After It Has Been Software Disabled3378.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)3388.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI3388.4.8 Local APIC Version Register3388.5 Handling Local Interrupts3398.5.1 Local Vector Table3398.5.2 Valid Interrupt Vectors3428.5.3 Error Handling3438.5.4 APIC Timer3448.5.5 Local Interrupt Acceptance3468.6 Issuing Interprocessor Interrupts3468.6.1 Interrupt Command Register (ICR)3468.6.2 Determining IPI Destination3528.6.2.1 Physical Destination Mode3528.6.2.2 Logical Destination Mode3538.6.2.3 Broadcast/Self Delivery Mode3558.6.2.4 Lowest Priority Delivery Mode3558.6.3 IPI Delivery and Acceptance3568.7 System and APIC Bus Arbitration3568.8 Handling Interrupts3578.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors3578.8.2 Interrupt Handling with the P6 Family and Pentium Processors3588.8.3 Interrupt, Task, and Processor Priority3608.8.3.1 Task and Processor Priorities3618.8.4 Interrupt Acceptance for Fixed Interrupts3628.8.5 Signaling Interrupt Servicing Completion3648.8.6 Task Priority in IA-32e Mode3648.8.6.1 Interaction of Task Priorities between CR8 and APIC3658.9 Spurious Interrupt3658.10 APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors)3678.10.1 Bus Message Formats3678.11 Message Signalled Interrupts3678.11.1 Message Address Register Format3688.11.2 Message Data Register Format369CHAPTER 9 Processor Management and Initialization3759.1 Initialization Overview3759.1.1 Processor State After Reset3769.1.2 Processor Built-In Self-Test (BIST)3769.1.3 Model and Stepping Information3799.1.4 First Instruction Executed3809.2 x87 FPU Initialization3809.2.1 Configuring the x87 FPU Environment3809.2.2 Setting the Processor for x87 FPU Software Emulation3819.3 Cache Enabling3829.4 Model-Specific Registers (MSRs)3839.5 Memory Type Range Registers (MTRRs)3839.6 Initializing SSE/SSE2/SSE3 Extensions3849.7 Software Initialization for Real-Address Mode Operation3849.7.1 Real-Address Mode IDT3859.7.2 NMI Interrupt Handling3859.8 Software Initialization for Protected-Mode Operation3859.8.1 Protected-Mode System Data Structures3869.8.2 Initializing Protected-Mode Exceptions and Interrupts3879.8.3 Initializing Paging3879.8.4 Initializing Multitasking3879.8.5 Initializing IA-32e Mode3889.8.5.1 IA-32e Mode System Data Structures3899.8.5.2 IA-32e Mode Interrupts and Exceptions3899.8.5.3 64-bit Mode and Compatibility Mode Operation3899.8.5.4 Switching Out of IA-32e Mode Operation3909.9 Mode Switching3919.9.1 Switching to Protected Mode3919.9.2 Switching Back to Real-Address Mode3929.10 Initialization and Mode Switching Example3949.10.1 Assembler Usage3969.10.2 STARTUP.ASM Listing3979.10.3 MAIN.ASM Source Code4079.10.4 Supporting Files4079.11 Microcode Update Facilities4099.11.1 Microcode Update4109.11.2 Optional Extended Signature Table4149.11.3 Processor Identification4159.11.4 Platform Identification4169.11.5 Microcode Update Checksum4179.11.6 Microcode Update Loader4189.11.6.1 Hard Resets in Update Loading4199.11.6.2 Update in a Multiprocessor System4199.11.6.3 Update in a System Supporting Intel Hyper-Threading Technology4209.11.6.4 Update in a System Supporting Dual-Core Technology4209.11.6.5 Update Loader Enhancements4209.11.7 Update Signature and Verification4209.11.7.1 Determining the Signature4219.11.7.2 Authenticating the Update4229.11.8 Pentium 4, Intel Xeon, and P6 Family Processor Microcode Update Specifications4239.11.8.1 Responsibilities of the BIOS4239.11.8.2 Responsibilities of the Calling Program4259.11.8.3 Microcode Update Functions4289.11.8.4 INT 15H-based Interface4299.11.8.5 Function 00H-Presence Test4299.11.8.6 Function 01H-Write Microcode Update Data4309.11.8.7 Function 02H-Microcode Update Control4359.11.8.8 Function 03H-Read Microcode Update Data4369.11.8.9 Return Codes437CHAPTER 10 Memory Cache Control44110.1 Internal Caches, TLBs, and Buffers44110.2 Caching Terminology44410.3 Methods of Caching Available44510.3.1 Buffering of Write Combining Memory Locations44810.3.2 Choosing a Memory Type44910.4 Cache Control Protocol45010.5 Cache Control45010.5.1 Cache Control Registers and Bits45110.5.2 Precedence of Cache Controls45510.5.2.1 Selecting Memory Types for Pentium Pro and Pentium II Processors45610.5.2.2 Selecting Memory Types for Pentium 4, Intel Xeon, and Pentium III Processors45710.5.2.3 Writing Values Across Pages with Different Memory Types45810.5.3 Preventing Caching45810.5.4 Disabling and Enabling the L3 Cache45910.5.5 Cache Management Instructions45910.5.6 L1 Data Cache Context Mode46010.5.6.1 Adaptive Mode46110.5.6.2 Shared Mode46110.6 Self-Modifying Code46110.7 Implicit Caching (Pentium 4, Intel Xeon, and P6 Family Processors)46210.8 Explicit Caching46210.9 Invalidating the Translation Lookaside Buffers (TLBs)46310.10 Store Buffer46410.11 Memory Type Range Registers (MTRRs)46410.11.1 MTRR Feature Identification46610.11.2 Setting Memory Ranges with MTRRs46710.11.2.1 IA32_MTRR_DEF_TYPE MSR46710.11.2.2 Fixed Range MTRRs46810.11.2.3 Variable Range MTRRs46910.11.3 Example Base and Mask Calculations47210.11.3.1 Base and Mask Calculations with Intel EM64T47310.11.4 Range Size and Alignment Requirement47410.11.4.1 MTRR Precedences47410.11.5 MTRR Initialization47510.11.6 Remapping Memory Types47510.11.7 MTRR Maintenance Programming Interface47610.11.7.1 MemTypeGet() Function47610.11.7.2 MemTypeSet() Function47710.11.8 MTRR Considerations in MP Systems47910.11.9 Large Page Size Considerations48010.12 Page Attribute Table (PAT)48110.12.1 Detecting Support for the PAT Feature48110.12.2 IA32_CR_PAT MSR48210.12.3 Selecting a Memory Type from the PAT48310.12.4 Programming the PAT48310.12.5 PAT Compatibility with Earlier IA-32 Processors485CHAPTER 11 Intel® MMX™ Technology System Programming48911.1 Emulation of the MMX Instruction Set48911.2 The MMX State and MMX Register Aliasing48911.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word49111.3 Saving and Restoring the MMX State and Registers49211.4 Saving MMX State on Task or Context Switches49311.5. EXCEPTIONS That Can Occur When Executing MMX Instructions49311.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions49411.6 Debugging MMX Code494CHAPTER 12 SSE, SSE2 and SSE3 System Programming49912.1 Providing Operating System Support for SSE/SSE2/SSE3 Extensions49912.1.1 Adding Support to an Operating System for SSE/SSE2/SSE3 Extensions49912.1.2 Checking for SSE/SSE2/SSE3 Extension Support50012.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions50012.1.4 Initialization of the SSE/SSE2/SSE3 Extensions50012.1.5 Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE/SSE2/SSE3 Instructions50212.1.6 Providing an Handler for the SIMD Floating-Point Exception (#XF)50312.1.6.1 Numeric Error flag and IGNNE#50412.2 Emulation of SSE/SSE2/SSE3 Extensions50412.3 Saving and Restoring the SSE/SSE2/SSE3 State50412.4 Saving the SSE/SSE2/SSE3 State on Task or Context Switches50512.5 Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and SSE/SSE2/SSE3 state on Task or Context Switches50512.5.1. Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE, SSE2 and SSE3 State506CHAPTER 13 Power and Thermal Management51113.1 Enhanced Intel Speedstep® Technology51113.1.1 Software Interface For Initiating Performance State Transitions51113.2 P-State Hardware Coordination51213.3 MWAIT Extensions for Advanced Power Management51413.4 Thermal Monitoring and Protection51513.4.1 Catastrophic Shutdown Detector51613.4.2 Thermal Monitor51613.4.2.1 Thermal Monitor 151613.4.2.2 Thermal Monitor 251613.4.2.3 Two Methods for Enabling TM251613.4.2.4 Performance State Transitions and Thermal Monitoring51713.4.2.5 Thermal Status Information51813.4.3 Software Controlled Clock Modulation51913.4.4 Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities52113.4.5 On Die Digital Thermal Sensors52113.4.5.1 Digital Thermal Sensor Enumeration52113.4.5.2 Reading the Digital Sensor521CHAPTER 14 Machine-Check Architecture52714.1 Machine-Check Exceptions and Architecture52714.2 Compatibility with Pentium Processor52714.3 Machine-Check MSRs52814.3.1 Machine-Check Global Control MSRs52814.3.1.1 IA32_MCG_CAP MSR (Pentium 4 and Intel Xeon Processors)52814.3.1.2 MCG_CAP MSR (P6 Family Processors)52914.3.1.3 IA32_MCG_STATUS MSR53014.3.1.4 IA32_MCG_CTL MSR53114.3.2 Error-Reporting Register Banks53114.3.2.1 IA32_MCi_CTL MSRs53114.3.2.2 IA32_MCi_STATUS MSRs53214.3.2.3 IA32_MCi_ADDR MSRs53314.3.2.4 IA32_MCi_MISC MSRs53414.3.2.5 IA32_MCG Extended Machine Check State MSRs53414.3.3 Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture53714.4 Machine-Check Availability53714.5 Machine-Check Initialization53714.6. Interpreting the MCA Error Codes53914.6.1 Simple Error Codes53914.6.2 Compound Error Codes54014.6.3 Machine-Check Error Codes Interpretation54314.7 Guidelines for Writing Machine-Check Software54314.7.1 Machine-Check Exception Handler54414.7.2 Enabling BINIT# Drive and BINIT# Observation54514.7.3 Pentium Processor Machine-Check Exception Handling54614.7.4 Logging Correctable Machine-Check Errors546CHAPTER 15 8086 Emulation55115.1 Real-Address Mode55115.1.1 Address Translation in Real-Address Mode55315.1.2 Registers Supported in Real-Address Mode55415.1.3 Instructions Supported in Real-Address Mode55415.1.4 Interrupt and Exception Handling55615.2 Virtual-8086 Mode55715.2.1 Enabling Virtual-8086 Mode55915.2.2 Structure of a Virtual-8086 Task55915.2.3 Paging of Virtual-8086 Tasks56015.2.4 Protection within a Virtual-8086 Task56115.2.5 Entering Virtual-8086 Mode56115.2.6 Leaving Virtual-8086 Mode56315.2.7 Sensitive Instructions56415.2.8 Virtual-8086 Mode I/O56415.2.8.1 I/O-Port-Mapped I/O56415.2.8.2 Memory-Mapped I/O56515.2.8.3 Special I/O Buffers56515.3 Interrupt and Exception Handling in Virtual-8086 Mode56515.3.1 Class 1-Hardware Interrupt and Exception Handling in Virtual-8086 Mode56715.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate56715.3.1.2 Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler56915.3.1.3 Handling an Interrupt or Exception Through a Task Gate57015.3.2 Class 2-Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism57015.3.3 Class 3-Software Interrupt Handling in Virtual-8086 Mode57315.3.3.1 Method 1: Software Interrupt Handling57515.3.3.2 Methods 2 and 3: Software Interrupt Handling57615.3.3.3 Method 4: Software Interrupt Handling57615.3.3.4 Method 5: Software Interrupt Handling57615.3.3.5 Method 6: Software Interrupt Handling57715.4 Protected-Mode Virtual Interrupts578CHAPTER 16 Mixing 16-Bit and 32-Bit Code58116.1 Defining 16-Bit and 32-Bit Program Modules58216.2 Mixing 16-Bit and 32-Bit Operations Within a Code Segment58216.3 Sharing Data Among Mixed-Size Code Segments58316.4 Transferring Control Among Mixed-Size Code Segments58416.4.1 Code-Segment Pointer Size58516.4.2 Stack Management for Control Transfer58516.4.2.1 Controlling the Operand-Size Attribute For a Call58716.4.2.2 Passing Parameters With a Gate58716.4.3 Interrupt Control Transfers58816.4.4 Parameter Translation58816.4.5 Writing Interface Procedures588CHAPTER 17 IA-32 Architecture Compatibility59317.1. IA-32 Processor Families and Categories59317.2. Reserved Bits59417.3. Enabling New Functions and Modes59417.4. Detecting the Presence of New Features Through Software59417.5. Intel MMX Technology59517.6. Streaming SIMD Extensions (SSE)59517.7. Streaming SIMD Extensions 2 (SSE2)59517.8. Streaming SIMD Extensions 3 (SSE3)59517.9. Hyper-Threading Technology59617.10. Dual-Core Technology59617.11. Specific Features of Dual-Core Processor59617.12. New Instructions In the Pentium and Later IA-32 Processors59617.12.1 Instructions Added Prior to the Pentium Processor59717.13. Obsolete Instructions59817.14. Undefined Opcodes59817.15. New Flags in the EFLAGS Register59817.15.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors59917.16. Stack Operations59917.16.1 PUSH SP59917.16.2 EFLAGS Pushed on the Stack60017.17. x87 FPU60017.17.1 Control Register CR0 Flags60017.17.2 x87 FPU Status Word60117.17.2.1 Condition Code Flags (C0 through C3)60117.17.2.2 Stack Fault Flag60117.17.3 x87 FPU Control Word60217.17.4 x87 FPU Tag Word60217.17.5 Data Types60217.17.5.1 NaNs60317.17.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats60317.17.6 Floating-Point Exceptions60317.17.6.1 Denormal Operand Exception (#D)60317.17.6.2 Numeric Overflow Exception (#O)60417.17.6.3 Numeric Underflow Exception (#U)60417.17.6.4 Exception Precedence60417.17.6.5 CS and EIP For FPU Exceptions60517.17.6.6 FPU Error Signals60517.17.6.7 Assertion of the FERR# Pin60517.17.6.8 Invalid Operation Exception On Denormals60617.17.6.9 Alignment Check Exceptions (#AC)60617.17.6.10 Segment Not Present Exception During FLDENV60617.17.6.11 Device Not Available Exception (#NM)60617.17.6.12 Coprocessor Segment Overrun Exception60617.17.6.13 General Protection Exception (#GP)60617.17.6.14 Floating-Point Error Exception (#MF)60717.17.7 Changes to Floating-Point Instructions60717.17.7.1 FDIV, FPREM, and FSQRT Instructions60717.17.7.2 FSCALE Instruction60717.17.7.3 FPREM1 Instruction60717.17.7.4 FPREM Instruction60717.17.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions60817.17.7.6 FPTAN Instruction60817.17.7.7 Stack Overflow60817.17.7.8 FSIN, FCOS, and FSINCOS Instructions60817.17.7.9 FPATAN Instruction60817.17.7.10 F2XM1 Instruction60817.17.7.11 FLD Instruction60817.17.7.12 FXTRACT Instruction60917.17.7.13 Load Constant Instructions60917.17.7.14 FSETPM Instruction60917.17.7.15 FXAM Instruction61017.17.7.16 FSAVE and FSTENV Instructions61017.17.8 Transcendental Instructions61017.17.9 Obsolete Instructions61017.17.10 WAIT/FWAIT Prefix Differences61017.17.11 Operands Split Across Segments and/or Pages61117.17.12 FPU Instruction Synchronization61117.18. Serializing Instructions61117.19. FPU and Math Coprocessor Initialization61117.19.1 Intel® 387 and Intel® 287 Math Coprocessor Initialization61117.19.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization61217.20. Control Registers61317.21. Memory Management Facilities61517.21.1 New Memory Management Control Flags61517.21.1.1 Physical Memory Addressing Extension61517.21.1.2 Global Pages61517.21.1.3 Larger Page Sizes61517.21.2 CD and NW Cache Control Flags61517.21.3 Descriptor Types and Contents61617.21.4 Changes in Segment Descriptor Loads61617.22. Debug Facilities61617.22.1 Differences in Debug Register DR661617.22.2 Differences in Debug Register DR761617.22.3 Debug Registers DR4 and DR561717.23. Recognition of Breakpoints61717.24. Exceptions and/or Exception Conditions61717.24.1 Machine-Check Architecture61917.24.2 Priority OF Exceptions61917.25. Interrupts61917.25.1 Interrupt Propagation Delay61917.25.2 NMI Interrupts61917.25.3 IDT Limit62017.26. Advanced Programmable Interrupt Controller (APIC)62017.26.1 Software Visible Differences Between the Local APIC and the 82489DX62017.26.2 New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors62117.26.3 New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors62117.27. Task Switching and TSs62117.27.1 P6 Family and Pentium Processor TSS62217.27.2 TSS Selector Writes62217.27.3 Order of Reads/Writes to the TSS62217.27.4 Using A 16-Bit TSS with 32-Bit Constructs62217.27.5 Differences in I/O Map Base Addresses62217.28. Cache Management62317.28.1 Self-Modifying Code with Cache Enabled62417.28.2 Disabling the L3 Cache62417.29. Paging62517.29.1 Large Pages62517.29.2 PCD and PWT Flags62517.29.3 Enabling and Disabling Paging62517.30. Stack Operations62617.30.1 Selector Pushes and Pops62617.30.2 Error Code Pushes62717.30.3 Fault Handling Effects on the Stack62717.30.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate62717.31. Mixing 16- and 32-Bit Segments62717.32. Segment and Address Wraparound62817.32.1 Segment Wraparound62817.33. Store Buffers and Memory Ordering62917.34. Bus Locking63017.35. Bus Hold63117.36. Model-Specific Extensions to the IA-3263117.36.1 Model-Specific Registers63117.36.2 RDMSR and WRMSR Instructions63117.36.3 Memory Type Range Registers63217.36.4 Machine-Check Exception and Architecture63217.36.5 Performance-Monitoring Counters63317.37. Two Ways to Run Intel 286 Processor Tasks633Taille: 3 MoPages: 636Language: EnglishOuvrir le manuel
