Intel IA-32 Manuale Utente
3-22 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
3.6.2
Page Tables and Directories in the Absence of Intel EM64T
The information that the processor uses to translate linear addresses into physical addresses
(when paging is enabled) is contained in four data structures:
(when paging is enabled) is contained in four data structures:
•
Page directory — An array of 32-bit page-directory entries (PDEs) contained in a
4-KByte page. Up to 1024 page-directory entries can be held in a page directory.
4-KByte page. Up to 1024 page-directory entries can be held in a page directory.
•
Page table — An array of 32-bit page-table entries (PTEs) contained in a 4-KByte page.
Up to 1024 page-table entries can be held in a page table. (Page tables are not used for
2-MByte or 4-MByte pages. These page sizes are mapped directly from one or more page-
directory entries.)
Up to 1024 page-table entries can be held in a page table. (Page tables are not used for
2-MByte or 4-MByte pages. These page sizes are mapped directly from one or more page-
directory entries.)
•
Page — A 4-KByte, 2-MByte, or 4-MByte flat address space.
•
Page-Directory-Pointer Table — An array of four 64-bit entries, each of which points to
a page directory. This data structure is only used when the physical address extension is
enabled (see Section 3.8, “36-Bit Physical Addressing Using the PAE Paging
Mechanism”).
a page directory. This data structure is only used when the physical address extension is
enabled (see Section 3.8, “36-Bit Physical Addressing Using the PAE Paging
Mechanism”).
These tables provide access to either 4-KByte or 4-MByte pages when normal 32-bit physical
addressing is being used and to either 4-KByte or 2-MByte pages or 4-MByte pages only when
extended (36-bit) physical addressing is being used.
addressing is being used and to either 4-KByte or 2-MByte pages or 4-MByte pages only when
extended (36-bit) physical addressing is being used.
Table 3-3 shows the page size and physical address size obtained from various settings of the
paging control flags and the PSE-36 CPUID feature flag. Each page-directory entry contains a
PS (page size) flag that specifies whether the entry points to a page table whose entries in turn
point to 4-KByte pages (PS set to 0) or whether the page-directory entry points directly to a
4-MByte (PSE and PS set to 1) or 2-MByte page (PAE and PS set to 1).
paging control flags and the PSE-36 CPUID feature flag. Each page-directory entry contains a
PS (page size) flag that specifies whether the entry points to a page table whose entries in turn
point to 4-KByte pages (PS set to 0) or whether the page-directory entry points directly to a
4-MByte (PSE and PS set to 1) or 2-MByte page (PAE and PS set to 1).
3.7
PAGE TRANSLATION USING 32-BIT PHYSICAL
ADDRESSING
ADDRESSING
The following sections describe the IA-32 architecture’s page translation mechanism when using
32-bit physical addresses and a maximum physical address space of 4 GBytes. The 32-bit phys-
ical addressing described applies to IA-32 processors that do not support Intel EM64T or when
the following situations are all true:
32-bit physical addresses and a maximum physical address space of 4 GBytes. The 32-bit phys-
ical addressing described applies to IA-32 processors that do not support Intel EM64T or when
the following situations are all true:
•
The processor supports Intel EM64T but IA-32e mode is not active.
•
PAE or PSE mechanism is not active.
Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism” and Section 3.9,
“36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” describe extensions to this
page translation mechanism to support 36-bit physical addresses and a maximum physical
address space of 64 GBytes.
“36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” describe extensions to this
page translation mechanism to support 36-bit physical addresses and a maximum physical
address space of 64 GBytes.