Intel IA-32 Manuale Utente
Vol. 3A 3-25
PROTECTED-MODE MEMORY MANAGEMENT
NOTE
(For the Pentium processor only.) When enabling or disabling large page
sizes, the TLBs must be invalidated (flushed) after the PSE flag in control
register CR4 has been set or cleared. Otherwise, incorrect page translation
might occur due to the processor using outdated page translation information
stored in the TLBs. See Section 10.9, “Invalidating the Translation Lookaside
Buffers (TLBs)”, for information on how to invalidate the TLBs.
sizes, the TLBs must be invalidated (flushed) after the PSE flag in control
register CR4 has been set or cleared. Otherwise, incorrect page translation
might occur due to the processor using outdated page translation information
stored in the TLBs. See Section 10.9, “Invalidating the Translation Lookaside
Buffers (TLBs)”, for information on how to invalidate the TLBs.
3.7.3
Mixing 4-KByte and 4-MByte Pages
When the PSE flag in CR4 is set, both 4-MByte pages and page tables for 4-KByte pages can
be accessed from the same page directory. If the PSE flag is clear, only page tables for 4-KByte
pages can be accessed (regardless of the setting of the PS flag in a page-directory entry).
be accessed from the same page directory. If the PSE flag is clear, only page tables for 4-KByte
pages can be accessed (regardless of the setting of the PS flag in a page-directory entry).
A typical example of mixing 4-KByte and 4-MByte pages is to place the operating system or
executive’s kernel in a large page to reduce TLB misses and thus improve overall system
performance.
executive’s kernel in a large page to reduce TLB misses and thus improve overall system
performance.
The processor maintains 4-MByte page entries and 4-KByte page entries in separate TLBs. So,
placing often used code such as the kernel in a large page, frees up 4-KByte-page TLB entries
for application programs and tasks.
placing often used code such as the kernel in a large page, frees up 4-KByte-page TLB entries
for application programs and tasks.
3.7.4
Memory Aliasing
The IA-32 architecture permits memory aliasing by allowing two page-directory entries to point
to a common page-table entry. Software that needs to implement memory aliasing in this manner
must manage the consistency of the accessed and dirty bits in the page-directory and page-table
entries. Allowing the accessed and dirty bits for the two page-directory entries to become incon-
sistent may lead to a processor deadlock.
to a common page-table entry. Software that needs to implement memory aliasing in this manner
must manage the consistency of the accessed and dirty bits in the page-directory and page-table
entries. Allowing the accessed and dirty bits for the two page-directory entries to become incon-
sistent may lead to a processor deadlock.
3.7.5
Base Address of the Page Directory
The physical address of the current page directory is stored in the CR3 register (also called the
page directory base register or PDBR). (See Figure 2-6 and Section 2.5, “Control Registers”, for
more information on the PDBR.) If paging is to be used, the PDBR must be loaded as part of the
processor initialization process (prior to enabling paging). The PDBR can then be changed
either explicitly by loading a new value in CR3 with a MOV instruction or implicitly as part of
a task switch. (See Section 6.2.1, “Task-State Segment (TSS)”, for a description of how the
contents of the CR3 register is set for a task.)
page directory base register or PDBR). (See Figure 2-6 and Section 2.5, “Control Registers”, for
more information on the PDBR.) If paging is to be used, the PDBR must be loaded as part of the
processor initialization process (prior to enabling paging). The PDBR can then be changed
either explicitly by loading a new value in CR3 with a MOV instruction or implicitly as part of
a task switch. (See Section 6.2.1, “Task-State Segment (TSS)”, for a description of how the
contents of the CR3 register is set for a task.)
There is no present flag in the PDBR for the page directory. The page directory may be not-
present (paged out of physical memory) while its associated task is suspended, but the operating
system must ensure that the page directory indicated by the PDBR image in a task's TSS is
present in physical memory before the task is dispatched. The page directory must also remain
in memory as long as the task is active.
present (paged out of physical memory) while its associated task is suspended, but the operating
system must ensure that the page directory indicated by the PDBR image in a task's TSS is
present in physical memory before the task is dispatched. The page directory must also remain
in memory as long as the task is active.