Intel IA-32 Manuale Utente
Vol. 3A 3-37
PROTECTED-MODE MEMORY MANAGEMENT
Access (A) and dirty (D) flags (bits 5 and 6) are provided for table entries that point to pages.
Bits 9, 10, and 11 in all the table entries for the physical address extension are available for use
by software. (When the present flag is clear, bits 1 through 63 are available to software.) All bits
in Figure 3-14 that are marked reserved or 0 should be set to 0 by software and not accessed by
software. When the PSE and/or PAE flags in control register CR4 are set, the processor gener-
ates a page fault (#PF) if reserved bits in page-directory and page-table entries are not set to 0,
and it generates a general-protection exception (#GP) if reserved bits in a page-directory-
pointer-table entry are not set to 0.
by software. (When the present flag is clear, bits 1 through 63 are available to software.) All bits
in Figure 3-14 that are marked reserved or 0 should be set to 0 by software and not accessed by
software. When the PSE and/or PAE flags in control register CR4 are set, the processor gener-
ates a page fault (#PF) if reserved bits in page-directory and page-table entries are not set to 0,
and it generates a general-protection exception (#GP) if reserved bits in a page-directory-
pointer-table entry are not set to 0.
3.9
36-BIT PHYSICAL ADDRESSING USING THE PSE-36
PAGING MECHANISM
PAGING MECHANISM
The PSE-36 paging mechanism provides an alternate method (from the PAE mechanism) of
extending physical memory addressing to 36 bits. This mechanism uses the page size extension
(PSE) mode and a modified page-directory table to map 4-MByte pages into a 64-GByte phys-
ical address space. As with the PAE mechanism, the processor provides 4 additional address line
pins to accommodate the additional address bits.
extending physical memory addressing to 36 bits. This mechanism uses the page size extension
(PSE) mode and a modified page-directory table to map 4-MByte pages into a 64-GByte phys-
ical address space. As with the PAE mechanism, the processor provides 4 additional address line
pins to accommodate the additional address bits.
The PSE-36 mechanism was introduced into the IA-32 architecture with the Pentium III proces-
sors. The availability of this feature is indicated with the PSE-36 feature bit (bit 17 of the EDX
register when the CPUID instruction is executed with a source operand of 1).
sors. The availability of this feature is indicated with the PSE-36 feature bit (bit 17 of the EDX
register when the CPUID instruction is executed with a source operand of 1).
As is shown in Table 3-3, the following flags must be set or cleared to enable the PSE-36 paging
mechanism:
mechanism:
•
PSE-36 CPUID feature flag — When set, it indicates the availability of the PSE-36
paging mechanism on the IA-32 processor on which the CPUID instruction is executed.
paging mechanism on the IA-32 processor on which the CPUID instruction is executed.
•
PG flag (bit 31) in register CR0 — Set to 1 to enable paging.
•
PAE flag (bit 5) in control register CR4 — Clear to 0 to disable the PAE paging
mechanism.
mechanism.
•
PSE flag (bit 4) in control register CR4 and the PS flag in PDE — Set to 1 to enable the
page size extension for 4-MByte pages.
page size extension for 4-MByte pages.
•
Or the PSE flag (bit 4) in control register CR4 — Set to 1 and the PS flag (bit 7) in
PDE— Set to 0 to enable 4-KByte pages with 32-bit addressing (below 4 GBytes).
PDE— Set to 0 to enable 4-KByte pages with 32-bit addressing (below 4 GBytes).
Figure 3-22 shows how the expanded page directory entry can be used to map a 32-bit linear
address to a 36-bit physical address. Here, the linear address is divided into two sections:
address to a 36-bit physical address. Here, the linear address is divided into two sections:
•
Page directory entry — Bits 22 through 35 provide an offset to an entry in the page
directory. The selected entry provides the 14 most significant bits of a 36-bit address,
which locates the base physical address of a 4-MByte page.
directory. The selected entry provides the 14 most significant bits of a 36-bit address,
which locates the base physical address of a 4-MByte page.
•
Page offset — Bits 0 through 21 provides an offset to a physical address in the page.
This paging method can be used to map up to 1024 pages into a 64-GByte physical address
space.
space.