Intel IA-32 Manuale Utente
Vol. 3A 5-61
INTERRUPT AND EXCEPTION HANDLING
Interrupt 19—SIMD Floating-Point Exception (#XF)
Exception Class
Fault.
Description
Indicates the processor has detected an SSE/SSE2/SSE3 SIMD floating-point exception. The
appropriate status flag in the MXCSR register must be set and the particular exception
unmasked for this interrupt to be generated.
appropriate status flag in the MXCSR register must be set and the particular exception
unmasked for this interrupt to be generated.
There are six classes of numeric exception conditions that can occur while executing an SSE/
SSE2/SSE3 SIMD floating-point instruction:
SSE2/SSE3 SIMD floating-point instruction:
•
Invalid operation (#I)
•
Divide-by-zero (#Z)
•
Denormal operand (#D)
•
Numeric overflow (#O)
•
Numeric underflow (#U)
•
Inexact result (Precision) (#P)
The invalid operation, divide-by-zero, and denormal-operand exceptions are pre-computation
exceptions; that is, they are detected before any arithmetic operation occurs. The numeric under-
flow, numeric overflow, and inexact result exceptions are post-computational exceptions.
exceptions; that is, they are detected before any arithmetic operation occurs. The numeric under-
flow, numeric overflow, and inexact result exceptions are post-computational exceptions.
See "SIMD Floating-Point Exceptions", in Chapter 11, “Programming with Streaming SIMD
Extensions 2 (SSE3),” of the IA-32 Intel® Architecture Software Developer’s Manual, Volume 1,
for additional information about the SIMD floating-point exception classes.
Extensions 2 (SSE3),” of the IA-32 Intel® Architecture Software Developer’s Manual, Volume 1,
for additional information about the SIMD floating-point exception classes.
When a SIMD floating-point exception occurs, the processor does either of the following things:
•
It handles the exception automatically by producing the most reasonable result and
allowing program execution to continue undisturbed. This is the response to masked
exceptions.
allowing program execution to continue undisturbed. This is the response to masked
exceptions.
•
It generates a SIMD floating-point exception, which in turn invokes a software exception
handler. This is the response to unmasked exceptions.
handler. This is the response to unmasked exceptions.
Each of the six SIMD floating-point exception conditions has a corresponding flag bit and mask
bit in the MXCSR register. If an exception is masked (the corresponding mask bit in the MXCSR
register is set), the processor takes an appropriate automatic default action and continues with
the computation. If the exception is unmasked (the corresponding mask bit is clear) and the
operating system supports SIMD floating-point exceptions (the OSXMMEXCPT flag in control
register CR4 is set), a software exception handler is invoked through a SIMD floating-point
exception. If the exception is unmasked and the OSXMMEXCPT bit is clear (indicating that the
operating system does not support unmasked SIMD floating-point exceptions), an invalid
opcode exception (#UD) is signaled instead of a SIMD floating-point exception.
bit in the MXCSR register. If an exception is masked (the corresponding mask bit in the MXCSR
register is set), the processor takes an appropriate automatic default action and continues with
the computation. If the exception is unmasked (the corresponding mask bit is clear) and the
operating system supports SIMD floating-point exceptions (the OSXMMEXCPT flag in control
register CR4 is set), a software exception handler is invoked through a SIMD floating-point
exception. If the exception is unmasked and the OSXMMEXCPT bit is clear (indicating that the
operating system does not support unmasked SIMD floating-point exceptions), an invalid
opcode exception (#UD) is signaled instead of a SIMD floating-point exception.