Intel IA-32 Manuale Utente
Vol. 3A 7-13
MULTIPLE-PROCESSOR MANAGEMENT
It is recommended that software written to run on Pentium 4, Intel Xeon, and P6 family proces-
sors assume the processor-ordering model or a weaker memory-ordering model. The Pentium 4,
Intel Xeon, and P6 family processors do not implement a strong memory-ordering model, except
when using the UC memory type. Despite the fact that Pentium 4, Intel Xeon, and P6 family
processors support processor ordering, Intel does not guarantee that future processors will
support this model. To make software portable to future processors, it is recommended that oper-
ating systems provide critical region and resource control constructs and API’s (application
program interfaces) based on I/O, locking, and/or serializing instructions be used to synchronize
access to shared areas of memory in multiple-processor systems. Also, software should not
depend on processor ordering in situations where the system hardware does not support this
memory-ordering model.
sors assume the processor-ordering model or a weaker memory-ordering model. The Pentium 4,
Intel Xeon, and P6 family processors do not implement a strong memory-ordering model, except
when using the UC memory type. Despite the fact that Pentium 4, Intel Xeon, and P6 family
processors support processor ordering, Intel does not guarantee that future processors will
support this model. To make software portable to future processors, it is recommended that oper-
ating systems provide critical region and resource control constructs and API’s (application
program interfaces) based on I/O, locking, and/or serializing instructions be used to synchronize
access to shared areas of memory in multiple-processor systems. Also, software should not
depend on processor ordering in situations where the system hardware does not support this
memory-ordering model.
7.3
PROPAGATION OF PAGE TABLE AND PAGE DIRECTORY
ENTRY CHANGES TO MULTIPLE PROCESSORS
ENTRY CHANGES TO MULTIPLE PROCESSORS
In a multiprocessor system, when one processor changes a page table or page directory entry,
the changes must also be propagated to all the other processors. This process is commonly
referred to as “TLB shootdown.” The propagation of changes to page table or page directory
entries can be done using memory-based semaphores and/or interprocessor interrupts (IPI)
between processors. For example, a simple but algorithmic correct TLB shootdown sequence
for a IA-32 processor is as follows:
the changes must also be propagated to all the other processors. This process is commonly
referred to as “TLB shootdown.” The propagation of changes to page table or page directory
entries can be done using memory-based semaphores and/or interprocessor interrupts (IPI)
between processors. For example, a simple but algorithmic correct TLB shootdown sequence
for a IA-32 processor is as follows:
1.
Begin barrier — Stop all but one processor; that is, cause all but one to HALT or stop in a
spin loop.
spin loop.
2.
Let the active processor change the necessary PTEs and/or PDEs.
3.
Let all processors invalidate the PTEs and PDEs modified in their TLBs.
4.
End barrier — Resume all processors; resume general processing.
Alternate, performance-optimized, TLB shootdown algorithms may be developed; however,
care must be taken by the developers to ensure that either of the following conditions are met:
care must be taken by the developers to ensure that either of the following conditions are met:
•
Different TLB mappings are not used on different processors during the update process.
•
The operating system is prepared to deal with the case where processors are using the stale
mapping during the update process.
mapping during the update process.