Intel IA-32 Manuale Utente

8-20 Vol. 3A

The ESR is a write/read register. A write (of any value) to the ESR must be done just prior to
reading the ESR to update the register. This initial write causes the ESR contents to be updated
with the latest error status. Back-to-back writes clear the ESR register. 

After an error bit is set in the register, it remains set until the register is cleared. Setting the mask
bit for the LVT error register prevents errors from being recorded in the ESR; however, the state
of the ESR before the mask bit was set is maintained.

The local APIC unit contains a 32-bit programmable timer that is available to software to time
events or operations. This timer is set up by programming four registers: the divide configura-
tion register (see Figure 8-10), the initial-count and current-count registers (see Figure 8-11),
and the LVT timer register (see Figure 8-8). 

Address: FEE0 0280H
Value after reset: 0H

31

0

Reserved

7

8

1

2

3

4

5

6

Illegal Register Address

1

Received Illegal Vector
Send Illegal Vector
Reserved
Receive Accept Error

2

Send Accept Error

2

Receive Checksum Error

2

Send Checksum Error

2

2. Only used in the P6 family and Pentium processors;

reserved in the Pentium 4 and Intel Xeon processors.

1. Only used in the Pentium 4, Intel Xeon, and P6 family

processors; reserved in the Pentium processor.