Intel IA-32 Manuale Utente
9-44 Vol. 3A
PROCESSOR MANAGEMENT AND INITIALIZATION
Example 9-7. Pseudo Code Example of Checksum Test
N
← 512
If (Update.DataSize != 00000000H)
N
← Update.TotalSize / 4
ChkSum
← 0
For (I
← 0; I < N; I++)
{
ChkSum
← ChkSum + MicrocodeUpdate[I]
}
If (ChkSum == 00000000H)
Success
Else
Fail
9.11.6
Microcode Update Loader
This section describes an update loader used to load an update into a Pentium 4, Intel Xeon, or
P6 family processor. It also discusses the requirements placed on the BIOS to ensure proper
loading. The update loader described contains the minimal instructions needed to load an
update. The specific instruction sequence that is required to load an update is dependent upon
the loader revision field contained within the update header. This revision is expected to change
infrequently (potentially, only when new processor models are introduced).
P6 family processor. It also discusses the requirements placed on the BIOS to ensure proper
loading. The update loader described contains the minimal instructions needed to load an
update. The specific instruction sequence that is required to load an update is dependent upon
the loader revision field contained within the update header. This revision is expected to change
infrequently (potentially, only when new processor models are introduced).
Example 9-8 below represents the update loader with a loader revision of 00000001H. Note that
the microcode update must be aligned on a 16-byte boundary.
the microcode update must be aligned on a 16-byte boundary.
Example 9-8. Assembly Code Example of Simple Microcode Update Loader
mov
ecx,79h
; MSR to read in ECX
xor
eax,eax
; clear EAX
xor
ebx,ebx
; clear EBX
mov
ax,cs
; Segment of microcode update
shl
eax,4
mov
bx,offset Update
; Offset of microcode update
add
eax,ebx
; Linear Address of Update in EAX
add
eax,48d
; Offset of the Update Data within the Update
xor
edx,edx
; Zero in EDX
WRMSR
; microcode update trigger