Intel IA-32 Manuale Utente
10-4 Vol. 3A
MEMORY CACHE CONTROL
The trace cache in the Pentium 4 and Intel Xeon processors is an integral part of the Intel
NetBurst microarchitecture and is available in all execution modes: protected mode, system
management mode (SMM), and real-address mode. The L1,L2, and L3 caches are also available
in all execution modes; however, use of them must be handled carefully in SMM (see Section
24.4.2, “SMRAM Caching”).
NetBurst microarchitecture and is available in all execution modes: protected mode, system
management mode (SMM), and real-address mode. The L1,L2, and L3 caches are also available
in all execution modes; however, use of them must be handled carefully in SMM (see Section
24.4.2, “SMRAM Caching”).
The TLBs store the most recently used page-directory and page-table entries. They speed up
memory accesses when paging is enabled by reducing the number of memory accesses that are
required to read the page tables stored in system memory. The TLBs are divided into four
groups: instruction TLBs for 4-KByte pages, data TLBs for 4-KByte pages; instruction TLBs
for large pages (2-MByte or 4-MByte pages), and data TLBs for large pages. The TLBs are
normally active only in protected mode with paging enabled. When paging is disabled or the
processor is in real-address mode, the TLBs maintain their contents until explicitly or implicitly
flushed (see Section 10.9, “Invalidating the Translation Lookaside Buffers (TLBs)”).
memory accesses when paging is enabled by reducing the number of memory accesses that are
required to read the page tables stored in system memory. The TLBs are divided into four
groups: instruction TLBs for 4-KByte pages, data TLBs for 4-KByte pages; instruction TLBs
for large pages (2-MByte or 4-MByte pages), and data TLBs for large pages. The TLBs are
normally active only in protected mode with paging enabled. When paging is disabled or the
processor is in real-address mode, the TLBs maintain their contents until explicitly or implicitly
flushed (see Section 10.9, “Invalidating the Translation Lookaside Buffers (TLBs)”).
The store buffer is associated with the processors instruction execution units. It allows writes to
system memory and/or the internal caches to be saved and in some cases combined to optimize
the processor’s bus accesses. The store buffer is always enabled in all execution modes.
system memory and/or the internal caches to be saved and in some cases combined to optimize
the processor’s bus accesses. The store buffer is always enabled in all execution modes.
The processor’s caches are for the most part transparent to software. When enabled, instructions
and data flow through these caches without the need for explicit software control. However,
knowledge of the behavior of these caches may be useful in optimizing software performance.
For example, knowledge of cache dimensions and replacement algorithms gives an indication
of how large of a data structure can be operated on at once without causing cache thrashing.
and data flow through these caches without the need for explicit software control. However,
knowledge of the behavior of these caches may be useful in optimizing software performance.
For example, knowledge of cache dimensions and replacement algorithms gives an indication
of how large of a data structure can be operated on at once without causing cache thrashing.
In multiprocessor systems, maintenance of cache consistency may, in rare circumstances,
require intervention by system software. For these rare cases, the processor provides privileged
cache control instructions for use in flushing caches and forcing memory ordering.
require intervention by system software. For these rare cases, the processor provides privileged
cache control instructions for use in flushing caches and forcing memory ordering.
The Pentium III, Pentium 4, and Intel Xeon processors introduced several instructions that soft-
ware can use to improve the performance of the L1, L2, and L3 caches, including the
PREFETCHh and CLFLUSH instructions and the non-temporal move instructions (MOVNTI,
MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD). The use of these instructions are
discussed in Section 10.5.5, “Cache Management Instructions.”
ware can use to improve the performance of the L1, L2, and L3 caches, including the
PREFETCHh and CLFLUSH instructions and the non-temporal move instructions (MOVNTI,
MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD). The use of these instructions are
discussed in Section 10.5.5, “Cache Management Instructions.”
10.2
CACHING TERMINOLOGY
The IA-32 architecture (beginning with the Pentium processor) uses the MESI (modified, exclu-
sive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in
other processors (see Section 10.4, “Cache Control Protocol”).
sive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in
other processors (see Section 10.4, “Cache Control Protocol”).
When the processor recognizes that an operand being read from memory is cacheable, the
processor reads an entire cache line into the appropriate cache (L1, L2, L3, or all). This operation
is called a cache line fill. If the memory location containing that operand is still cached the next
time the processor attempts to access the operand, the processor can read the operand from the
cache instead of going back to memory. This operation is called a cache hit.
processor reads an entire cache line into the appropriate cache (L1, L2, L3, or all). This operation
is called a cache line fill. If the memory location containing that operand is still cached the next
time the processor attempts to access the operand, the processor can read the operand from the
cache instead of going back to memory. This operation is called a cache hit.