Intel IA-32 Manuale Utente
Vol. 3A 10-19
MEMORY CACHE CONTROL
3.
Disable the MTRRs and set the default memory type to uncached or set all MTRRs for the
uncached memory type (see the discussion of the discussion of the TYPE field and the E
flag in Section 10.11.2.1, “IA32_MTRR_DEF_TYPE MSR”).
uncached memory type (see the discussion of the discussion of the TYPE field and the E
flag in Section 10.11.2.1, “IA32_MTRR_DEF_TYPE MSR”).
The caches must be flushed (step 2) after the CD flag is set to insure system memory coherency.
If the caches are not flushed, cache hits on reads will still occur and data will be read from valid
cache lines.
If the caches are not flushed, cache hits on reads will still occur and data will be read from valid
cache lines.
NOTES
Setting the CD flag in control register CR0 modifies the processor’s caching
behaviour as indicated in Table 10-5, but it does not force the effective
memory type for all physical memory to be UC nor does it force strict
memory ordering. To force the UC memory type and strict memory ordering
on all of physical memory, either the MTRRs must all be programmed for the
UC memory type or they must be disabled.
behaviour as indicated in Table 10-5, but it does not force the effective
memory type for all physical memory to be UC nor does it force strict
memory ordering. To force the UC memory type and strict memory ordering
on all of physical memory, either the MTRRs must all be programmed for the
UC memory type or they must be disabled.
For the Pentium 4 and Intel Xeon processors, after the sequence of steps
given above has been executed, the cache lines containing the code between
the end of the WBINVD instruction and before the MTRRS have actually
been disabled may be retained in the cache hierarchy. Here, to remove code
from the cache completely, a second WBINVD instruction must be executed
after the MTRRs have been disabled.
given above has been executed, the cache lines containing the code between
the end of the WBINVD instruction and before the MTRRS have actually
been disabled may be retained in the cache hierarchy. Here, to remove code
from the cache completely, a second WBINVD instruction must be executed
after the MTRRs have been disabled.
10.5.4
Disabling and Enabling the L3 Cache
Third-level cache disable flag (bit 6 of the IA32_MISC_ENABLE MSR) allows the L3 cache
to be disabled and enabled, independently of the L1 and L2 caches. Prior to using this control to
disable or enable the L3 cache, software should disable and flush all the processor caches, as
described earlier in Section 10.5.3, “Preventing Caching,” to prevent of loss of information
stored in the L3 cache. After the L3 cache has been disabled or enabled, caching for the whole
processor can be restored.
to be disabled and enabled, independently of the L1 and L2 caches. Prior to using this control to
disable or enable the L3 cache, software should disable and flush all the processor caches, as
described earlier in Section 10.5.3, “Preventing Caching,” to prevent of loss of information
stored in the L3 cache. After the L3 cache has been disabled or enabled, caching for the whole
processor can be restored.
10.5.5
Cache Management Instructions
The IA-32 architecture provide several instructions for managing the L1, L2, and L3 caches. The
INVD, WBINVD, and WBINVD instructions are system instructions that operate on the L1, L2,
and L3 caches as a whole. The PREFETCHh and CLFLUSH instructions and the non-temporal
move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD), which
were introduced in SSE/SSE2 extensions, offer more granular control over caching.
INVD, WBINVD, and WBINVD instructions are system instructions that operate on the L1, L2,
and L3 caches as a whole. The PREFETCHh and CLFLUSH instructions and the non-temporal
move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD), which
were introduced in SSE/SSE2 extensions, offer more granular control over caching.
The INVD and WBINVD instructions are used to invalidate the contents of the L1, L2, and L3
caches. The INVD instruction invalidates all internal cache entries, then generates a special-
function bus cycle that indicates that external caches also should be invalidated. The INVD
instruction should be used with care. It does not force a write-back of modified cache lines;
therefore, data stored in the caches and not written back to system memory will be lost. Unless
there is a specific requirement or benefit to invalidating the caches without writing back the
caches. The INVD instruction invalidates all internal cache entries, then generates a special-
function bus cycle that indicates that external caches also should be invalidated. The INVD
instruction should be used with care. It does not force a write-back of modified cache lines;
therefore, data stored in the caches and not written back to system memory will be lost. Unless
there is a specific requirement or benefit to invalidating the caches without writing back the