Intel IA-32 Manuale Utente
Vol. 3A 11-5
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
NOTE
The IA-32 architecture does not support scanning the x87 FPU tag word and
then only saving valid entries.
then only saving valid entries.
11.4
SAVING MMX STATE ON TASK OR CONTEXT SWITCHES
When switching from one task or context to another, it is often necessary to save the MMX state.
As a general rule, if the existing task switching code for an operating system includes facilities
for saving the state of the x87 FPU, these facilities can also be relied upon to save the MMX
state, without rewriting the task switch code. This reliance is possible because the MMX state
is aliased to the x87 FPU state (see Section 11.2, “The MMX State and MMX Register
Aliasing”).
As a general rule, if the existing task switching code for an operating system includes facilities
for saving the state of the x87 FPU, these facilities can also be relied upon to save the MMX
state, without rewriting the task switch code. This reliance is possible because the MMX state
is aliased to the x87 FPU state (see Section 11.2, “The MMX State and MMX Register
Aliasing”).
With the introduction of the FXSAVE and FXRSTOR instructions and of SSE/SSE2/SSE3
extensions to the IA-32 architecture, it is possible (and more efficient) to create state saving
facilities in the operating system or executive that save the x87 FPU/MMX/SSE/SSE2/SSE3
state in one operation. Section 12.5, “Designing OS Facilities for AUTOMATICALLY Saving
x87 FPU, MMX, and SSE/SSE2/SSE3 state on Task or Context Switches,” describes how to
design such facilities. The techniques describes in this section can be adapted to saving only the
MMX and x87 FPU state if needed.
extensions to the IA-32 architecture, it is possible (and more efficient) to create state saving
facilities in the operating system or executive that save the x87 FPU/MMX/SSE/SSE2/SSE3
state in one operation. Section 12.5, “Designing OS Facilities for AUTOMATICALLY Saving
x87 FPU, MMX, and SSE/SSE2/SSE3 state on Task or Context Switches,” describes how to
design such facilities. The techniques describes in this section can be adapted to saving only the
MMX and x87 FPU state if needed.
11.5. EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX
INSTRUCTIONS
MMX instructions do not generate x87 FPU floating-point exceptions, nor do they affect the
processor’s status flags in the EFLAGS register or the x87 FPU status word. The following
exceptions can be generated during the execution of an MMX instruction:
processor’s status flags in the EFLAGS register or the x87 FPU status word. The following
exceptions can be generated during the execution of an MMX instruction:
•
Exceptions during memory accesses:
— Stack-segment fault (#SS).
— General protection (#GP).
— Page fault (#PF).
— Alignment check (#AC), if alignment checking is enabled.
•
System exceptions:
— Invalid Opcode (#UD), if the EM flag in control register CR0 is set when an MMX
instruction is executed (see Section 11.1, “Emulation of the MMX Instruction Set”).
— Device not available (#NM), if an MMX instruction is executed when the TS flag in
control register CR0 is set. (See Section 12.5.1., “Using the TS Flag to Control the
Saving of the x87 FPU, MMX, SSE, SSE2 and SSE3 State.”)
Saving of the x87 FPU, MMX, SSE, SSE2 and SSE3 State.”)
•
Floating-point error (#MF). (See Section 11.5.1, “Effect of MMX Instructions on Pending
x87 Floating-Point Exceptions.”)
x87 Floating-Point Exceptions.”)