Intel IA-32 Manuale Utente
Vol. 3A 12-5
SSE, SSE2 AND SSE3 SYSTEM PROGRAMMING
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System Exceptions:
— Invalid-opcode exception (#UD). This exception is generated when executing
SSE/SSE2/SSE3 instructions under the following conditions:
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SSE/SSE2/SSE3 feature flags returned by CPUID are set to 0. This condition does
not affect the CLFLUSH instruction.
not affect the CLFLUSH instruction.
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The CLFSH feature flag returned by the CPUID instruction is set to 0. This
exception condition only pertains to the execution of the CLFLUSH instruction.
exception condition only pertains to the execution of the CLFLUSH instruction.
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The EM flag (bit 2) in control register CR0 is set to 1, regardless of the value of
TS flag (bit 3) of CR0. This condition does not affect the PAUSE, PREFETCHh,
MOVNTI, SFENCE, LFENCE, MFENSE, and CLFLUSH instructions.
TS flag (bit 3) of CR0. This condition does not affect the PAUSE, PREFETCHh,
MOVNTI, SFENCE, LFENCE, MFENSE, and CLFLUSH instructions.
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The OSFXSR flag (bit 9) in control register CR4 is set to 0. This condition does
not affect the PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB,
PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW,
MASKMOVQ, MOVNTQ, MOVNTI, PAUSE, PREFETCHh, SFENCE,
LFENCE, MFENCE, and CLFLUSH instructions.
not affect the PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB,
PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW,
MASKMOVQ, MOVNTQ, MOVNTI, PAUSE, PREFETCHh, SFENCE,
LFENCE, MFENCE, and CLFLUSH instructions.
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Executing a instruction that causes a SIMD floating-point exception when the
OSXMMEXCPT flag (bit 10) in control register CR4 is set to 0. See Section
12.5.1., “Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE,
SSE2 and SSE3 State.”
OSXMMEXCPT flag (bit 10) in control register CR4 is set to 0. See Section
12.5.1., “Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE,
SSE2 and SSE3 State.”
— Device not available (#NM). This exception is generated by executing a
SSE/SSE2/SSE3 instruction when the TS flag (bit 3) of CR0 is set to 1.
Other exceptions can occur indirectly due to faulty execution of the above exceptions.
12.1.6
Providing an Handler for the SIMD Floating-Point
Exception (#XF)
Exception (#XF)
SSE/SSE2/SSE3 instructions do not generate numeric exceptions on packed integer operations.
They can generate the following numeric (SIMD floating-point) exceptions on packed and
scalar single-precision and double-precision floating-point operations.
They can generate the following numeric (SIMD floating-point) exceptions on packed and
scalar single-precision and double-precision floating-point operations.
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Invalid operation (#I)
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Divide-by-zero (#Z)
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Denormal operand (#D)
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Numeric overflow (#O)
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Numeric underflow (#U)
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Inexact result (Precision) (#P)
These SIMD floating-point exceptions (with the exception of the denormal operand exception)
are defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic and represent the
are defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic and represent the