Intel IA-32 Manuale Utente
13-2 Vol. 3A
POWER AND THERMAL MANAGEMENT
13.2
P-STATE HARDWARE COORDINATION
The Advanced Configuration and Power Interface (ACPI) defines performance states (P-state)
that are used facilitate system software’s ability to manage processor power consumption.
Different P-state correspond to different performance levels that are applied while the processor
is actively executing instructions. Enhanced Intel SpeedStep Technology supports P-state by
providing software interfaces that control the operating frequency and voltage of a processor.
that are used facilitate system software’s ability to manage processor power consumption.
Different P-state correspond to different performance levels that are applied while the processor
is actively executing instructions. Enhanced Intel SpeedStep Technology supports P-state by
providing software interfaces that control the operating frequency and voltage of a processor.
With multiple processor cores residing in the same physical package, hardware dependencies
may exist for a subset of logical processors on a platform. These dependencies may impose
requirements that impact coordination of P-state transitions. As a result, multi-core processors
may require an OS to provide additional software support for coordinating P-state transitions for
those subsets of logical processors.
may exist for a subset of logical processors on a platform. These dependencies may impose
requirements that impact coordination of P-state transitions. As a result, multi-core processors
may require an OS to provide additional software support for coordinating P-state transitions for
those subsets of logical processors.
A BIOS (following ACPI 3.0 specification) can choose to expose P-state as dependent and hard-
ware-coordinated to OS power management (OSPM) policy. To support OSPMs, multi-core
processors must have additional built-in support for P-state hardware coordination and feed-
back.
ware-coordinated to OS power management (OSPM) policy. To support OSPMs, multi-core
processors must have additional built-in support for P-state hardware coordination and feed-
back.
IA-32 processors with dependent P-state amongst a subset of logical processors permit hardware
coordination of P-state and provide a hardware-coordination feedback mechanism using
IA32_MPERF MSR and IA32_APERF MSR. See Figure 13-1 for an overview of the two 64-
bit MSRs and the bullets below for a detailed description:
coordination of P-state and provide a hardware-coordination feedback mechanism using
IA32_MPERF MSR and IA32_APERF MSR. See Figure 13-1 for an overview of the two 64-
bit MSRs and the bullets below for a detailed description:
•
Use CPUID to check the P-State hardware coordination feedback capability bit.
CPUID.06H.ECX[Bit 0] = 1 indicates IA32_MPERF MSR and IA32_APERF MSR are
present.
CPUID.06H.ECX[Bit 0] = 1 indicates IA32_MPERF MSR and IA32_APERF MSR are
present.
•
IA32_MPERF MSR (0xE7) increments in proportion to the maximum operating frequency
as indicated in the processor brand string.
as indicated in the processor brand string.
•
IA32_APERF MSR (0xE8) increments in proportion to actual performance, while
accounting for hardware coordination of P-state and TM1/TM2; or software initiated
throttling.
accounting for hardware coordination of P-state and TM1/TM2; or software initiated
throttling.
•
The MSRs are per logical processor; they measure performance only when the targeted
processor is in the C0 state.
processor is in the C0 state.
•
Only the IA32_APERF/IA32_MPERF ratio is architecturally defined; software should not
attach meaning to the content of the individual of IA32_APERF or IA32_MPERF MSRs.
attach meaning to the content of the individual of IA32_APERF or IA32_MPERF MSRs.
Figure 13-1. IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination
63
0
IA32_MPERF (Addr: E7H)
63
0
IA32_APERF (Addr: E8H)