Intel IA-32 Manuale Utente

14-8 Vol. 3A

The IA32_MCi_MISC MSR (called the MCi_MISC MSR in the P6 family processors) contains
additional information describing the machine-check error if the MISCV flag in the
IA32_MCi_STATUS register is set. The IA32_MCi_MISC_MSR is either not implemented or
does not contain additional information if the MISCV flag in the IA32_MCi_STATUS register
is clear. 

When not implemented in the processor, all reads and writes to this MSR will cause a general
protection exception. When implemented in a processor, these registers can be cleared by
explicitly writing all 0s to them; writing 1s to them causes a general-protection exception to be
generated. This register is not implemented in any of the error-reporting register banks for the
P6 family processors. 

The Pentium 4 and Intel Xeon processors implement a variable number of extended machine-
check state MSRs. The MCG_EXT_P flag in the IA32_MCG_CAP MSR indicates the presence
of these extended registers, and the MCG_EXT_CNT field indicates the number of these regis-
ters actually implemented. See Section 14.3.1.1, “IA32_MCG_CAP MSR (Pentium 4 and Intel
Xeon Processors).” See Table 14-1.

Figure 14-7.  IA32_MCi_ADDR MSR

IA32_MCG_EAX

180H

Contains state of the EAX register at the time of the machine-
check error.

IA32_MCG_EBX

181H

Contains state of the EBX register at the time of the machine-
check error.

Address

63

0

Reserved

35

36

Address

*

63

0

* 

Useful bits in this field depend on the address methodology in use when the 

the register state is saved.