Intel IA-32 Manuale Utente
Vol. 3A 14-11
MACHINE-CHECK ARCHITECTURE
14.3.3
Mapping of the Pentium
Processor Machine-Check Errors
to the Machine-Check Architecture
The Pentium processor reports machine-check errors using two registers: P5_MC_TYPE and
P5_MC_ADDR. The Pentium 4, Intel Xeon, and P6 family processors map these registers to the
IA32_MCi_STATUS and IA32_MCi_ADDR in the error-reporting register bank. This bank
reports on the same type of external bus errors reported in P5_MC_TYPE and P5_MC_ADDR.
P5_MC_ADDR. The Pentium 4, Intel Xeon, and P6 family processors map these registers to the
IA32_MCi_STATUS and IA32_MCi_ADDR in the error-reporting register bank. This bank
reports on the same type of external bus errors reported in P5_MC_TYPE and P5_MC_ADDR.
The information in these registers can then be accessed in two ways:
•
By reading the IA32_MCi_STATUS and IA32_MCi_ADDR registers as part of a general
machine-check exception handler written for Pentium 4 and P6 family processors.
machine-check exception handler written for Pentium 4 and P6 family processors.
•
By reading the P5_MC_TYPE and P5_MC_ADDR registers using the RDMSR
instruction.
instruction.
The second capability permits a machine-check exception handler written to run on a Pentium
processor to be run on a Pentium 4, Intel Xeon, or P6 family processor. There is a limitation in
that information returned by the Pentium 4, Intel Xeon, and P6 family processors is encoded
differently than information returned by the Pentium processor. To run a Pentium processor
machine-check exception handler on a Pentium 4, Intel Xeon, or P6 family processor; the
handler must be written to interpret P5_MC_TYPE encodings correctly.
processor to be run on a Pentium 4, Intel Xeon, or P6 family processor. There is a limitation in
that information returned by the Pentium 4, Intel Xeon, and P6 family processors is encoded
differently than information returned by the Pentium processor. To run a Pentium processor
machine-check exception handler on a Pentium 4, Intel Xeon, or P6 family processor; the
handler must be written to interpret P5_MC_TYPE encodings correctly.
14.4
MACHINE-CHECK AVAILABILITY
The machine-check architecture and machine-check exception (#MC) are model-specific
features. Software can execute the CPUID instruction to determine whether a processor imple-
ments these features. Following the execution of the CPUID instruction, the settings of the MCA
flag (bit 14) and MCE flag (bit 7) in EDX indicate whether the processor implements the
machine-check architecture and machine-check exception.
features. Software can execute the CPUID instruction to determine whether a processor imple-
ments these features. Following the execution of the CPUID instruction, the settings of the MCA
flag (bit 14) and MCE flag (bit 7) in EDX indicate whether the processor implements the
machine-check architecture and machine-check exception.
14.5
MACHINE-CHECK INITIALIZATION
To use the processors machine-check architecture, software must initialize the processor to acti-
vate the machine-check exception and the error-reporting mechanism.
vate the machine-check exception and the error-reporting mechanism.
Example 14-19 gives pseudocode for performing this initialization. This pseudocode checks for
the existence of the machine-check architecture and exception; it then enables machine-check
exception and the error-reporting register banks. The pseudocode shown is compatible with the
Pentium 4, Intel Xeon, P6 family, and Pentium processors.
the existence of the machine-check architecture and exception; it then enables machine-check
exception and the error-reporting register banks. The pseudocode shown is compatible with the
Pentium 4, Intel Xeon, P6 family, and Pentium processors.
Following power up or power cycling, IA32_MCi_STATUS registers are not guaranteed to have
valid data until after they are initially cleared to zero by software (as shown in the initialization
pseudocode in Example 14-19). In addition, when using P6 family processors, software must set
MCi_STATUS registers to zero when doing a soft-reset.
valid data until after they are initially cleared to zero by software (as shown in the initialization
pseudocode in Example 14-19). In addition, when using P6 family processors, software must set
MCi_STATUS registers to zero when doing a soft-reset.