Intel IA-32 Manuale Utente
Vol. 3A 15-17
8086 EMULATION
15.3.1
Class 1—Hardware Interrupt and Exception Handling
in Virtual-8086 Mode
in Virtual-8086 Mode
In virtual-8086 mode, the Pentium, P6 family, Pentium 4, and Intel Xeon processors handle
hardware interrupts and exceptions in the same manner as they are handled by the Intel486 and
Intel386 processors. They invoke the protected-mode interrupt or exception handler that the
interrupt or exception vector points to in the IDT. Here, the IDT entry must contain either a
32-bit trap or interrupt gate or a task gate. The following sections describe various ways that a
virtual-8086 mode interrupt or exception can be handled after the protected-mode handler has
been invoked.
hardware interrupts and exceptions in the same manner as they are handled by the Intel486 and
Intel386 processors. They invoke the protected-mode interrupt or exception handler that the
interrupt or exception vector points to in the IDT. Here, the IDT entry must contain either a
32-bit trap or interrupt gate or a task gate. The following sections describe various ways that a
virtual-8086 mode interrupt or exception can be handled after the protected-mode handler has
been invoked.
See Section 15.3.2, “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode
Using the Virtual Interrupt Mechanism”, for a description of the virtual interrupt mechanism that
is available for handling maskable hardware interrupts while in virtual-8086 mode. When this
mechanism is either not available or not enabled, maskable hardware interrupts are handled in
the same manner as exceptions, as described in the following sections.
Using the Virtual Interrupt Mechanism”, for a description of the virtual interrupt mechanism that
is available for handling maskable hardware interrupts while in virtual-8086 mode. When this
mechanism is either not available or not enabled, maskable hardware interrupts are handled in
the same manner as exceptions, as described in the following sections.
15.3.1.1
Handling an Interrupt or Exception Through a
Protected-Mode Trap or Interrupt Gate
Protected-Mode Trap or Interrupt Gate
When an interrupt or exception vector points to a 32-bit trap or interrupt gate in the IDT, the gate
must in turn point to a nonconforming, privilege-level 0, code segment. When accessing this
code segment, processor performs the following steps.
must in turn point to a nonconforming, privilege-level 0, code segment. When accessing this
code segment, processor performs the following steps.
1.
Switches to 32-bit protected mode and privilege level 0.
2.
Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS,
EFLAGS, ESP, SS, ES, DS, FS, and GS registers are saved (see Figure 15-4).
EFLAGS, ESP, SS, ES, DS, FS, and GS registers are saved (see Figure 15-4).
3.
Clears the segment registers. Saving the DS, ES, FS, and GS registers on the stack and then
clearing the registers lets the interrupt or exception handler safely save and restore these
registers regardless of the type segment selectors they contain (protected-mode or 8086-
style). The interrupt and exception handlers, which may be called in the context of either a
protected-mode task or a virtual-8086-mode task, can use the same code sequences for
saving and restoring the registers for any task. Clearing these registers before execution of
the IRET instruction does not cause a trap in the interrupt handler. Interrupt procedures that
expect values in the segment registers or that return values in the segment registers must
use the register images saved on the stack for privilege level 0.
clearing the registers lets the interrupt or exception handler safely save and restore these
registers regardless of the type segment selectors they contain (protected-mode or 8086-
style). The interrupt and exception handlers, which may be called in the context of either a
protected-mode task or a virtual-8086-mode task, can use the same code sequences for
saving and restoring the registers for any task. Clearing these registers before execution of
the IRET instruction does not cause a trap in the interrupt handler. Interrupt procedures that
expect values in the segment registers or that return values in the segment registers must
use the register images saved on the stack for privilege level 0.
4.
Clears VM, NT, RF and TF flags (in the EFLAGS register). If the gate is an interrupt gate,
clears the IF flag.
clears the IF flag.
5.
Begins executing the selected interrupt or exception handler.
If the trap or interrupt gate references a procedure in a conforming segment or in a segment at a
privilege level other than 0, the processor generates a general-protection exception (#GP). Here,
the error code is the segment selector of the code segment to which a call was attempted.
privilege level other than 0, the processor generates a general-protection exception (#GP). Here,
the error code is the segment selector of the code segment to which a call was attempted.