Intel IA-32 Manuale Utente
17-28 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
17.25.3 IDT Limit
The LIDT instruction can be used to set a limit on the size of the IDT. A double-fault exception
(#DF) is generated if an interrupt or exception attempts to read a vector beyond the limit. Shut-
down then occurs on the 32-bit IA-32 processors if the double-fault handler vector is beyond the
limit. (The 8086 processor does not have a shutdown mode nor a limit.)
(#DF) is generated if an interrupt or exception attempts to read a vector beyond the limit. Shut-
down then occurs on the 32-bit IA-32 processors if the double-fault handler vector is beyond the
limit. (The 8086 processor does not have a shutdown mode nor a limit.)
17.26. ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER
(APIC)
The Advanced Programmable Interrupt Controller (APIC), referred to in this book as the local
APIC, was introduced into the IA-32 processors with the Pentium processor (beginning with the
735/90 and 815/100 models) and is included in the Pentium 4, Intel Xeon, and P6 family proces-
sors. The features and functions of the local APIC are derived from the Intel 82489DX external
APIC, which was used with the Intel486 and early Pentium processors. Additional refinements
of the local APIC architecture were incorporated in the Pentium 4 and Intel Xeon processors.
APIC, was introduced into the IA-32 processors with the Pentium processor (beginning with the
735/90 and 815/100 models) and is included in the Pentium 4, Intel Xeon, and P6 family proces-
sors. The features and functions of the local APIC are derived from the Intel 82489DX external
APIC, which was used with the Intel486 and early Pentium processors. Additional refinements
of the local APIC architecture were incorporated in the Pentium 4 and Intel Xeon processors.
17.26.1 Software Visible Differences Between the Local APIC and
the 82489DX
The following features in the local APIC features differ from those found in the 82489DX
external APIC:
external APIC:
•
When the local APIC is disabled by clearing the APIC software enable/disable flag in the
spurious-interrupt vector MSR, the state of its internal registers are unaffected, except that
the mask bits in the LVT are all set to block local interrupts to the processor. Also, the local
APIC ceases accepting IPIs except for INIT, SMI, NMI, and start-up IPIs. In the 82489DX,
when the local unit is disabled, all the internal registers including the IRR, ISR and TMR
are cleared and the mask bits in the LVT are set. In this state, the 82489DX local unit will
accept only the reset deassert message.
spurious-interrupt vector MSR, the state of its internal registers are unaffected, except that
the mask bits in the LVT are all set to block local interrupts to the processor. Also, the local
APIC ceases accepting IPIs except for INIT, SMI, NMI, and start-up IPIs. In the 82489DX,
when the local unit is disabled, all the internal registers including the IRR, ISR and TMR
are cleared and the mask bits in the LVT are set. In this state, the 82489DX local unit will
accept only the reset deassert message.
•
In the local APIC, NMI and INIT (except for INIT deassert) are always treated as edge
triggered interrupts, even if programmed otherwise. In the 82489DX, these interrupts are
always level triggered.
triggered interrupts, even if programmed otherwise. In the 82489DX, these interrupts are
always level triggered.
•
In the local APIC, IPIs generated through the ICR are always treated as edge triggered
(except INIT Deassert). In the 82489DX, the ICR can be used to generate either edge or
level triggered IPIs.
(except INIT Deassert). In the 82489DX, the ICR can be used to generate either edge or
level triggered IPIs.
•
In the local APIC, the logical destination register supports 8 bits; in the 82489DX, it
supports 32 bits.
supports 32 bits.
•
In the local APIC, the APIC ID register is 4 bits wide; in the 82489DX, it is 8 bits wide.
•
The remote read delivery mode provided in the 82489DX and local APIC for Pentium
processors is not supported in the local APIC in the Pentium 4, Intel Xeon, and P6 family
processors.
processors is not supported in the local APIC in the Pentium 4, Intel Xeon, and P6 family
processors.