Intel IA-32 Manuale Utente

3-6 Vol. 3A

In IA-32e mode, the effects of segmentation depend on whether the processor is running in
compatibility mode or 64-bit mode. In compatibility mode, segmentation functions just as it
does using legacy 16-bit or 32-bit protected mode semantics.

In 64-bit mode, segmentation is generally (but not completely) disabled, creating a flat 64-bit
linear-address space. The processor treats the segment base of CS, DS, ES, SS as zero, creating
a linear address that is equal to the effective address. The FS and GS segments are exceptions.
These segment registers (which hold the segment base) can be used as an additional base regis-
ters in linear address calculations. They facilitate addressing local data and certain operating
system data structures. 

Note that the processor does not perform segment limit checks at runtime in 64-bit mode.

Paging can be used with any of the segmentation models described in Figures 3-2, 3-3, and 3-4.
The processor’s paging mechanism divides the linear address space (into which segments are
mapped) into pages (as shown in Figure 3-1). These linear-address-space pages are then mapped
to pages in the physical address space. The paging mechanism offers several page-level protec-
tion facilities that can be used with or instead of the segment-protection facilities. For example,
it lets read-write protection be enforced on a page-by-page basis. The paging mechanism also
provides two-level user-supervisor protection that can also be specified on a page-by-page basis.

In protected mode, the IA-32 architecture provides a normal physical address space of 4 GBytes
(2

32

 

bytes). This is the address space that the processor can address on its address bus. This

address space is flat (unsegmented), with addresses ranging continuously from 0 to
FFFFFFFFH. This physical address space can be mapped to read-write memory, read-only
memory, and memory mapped I/O. The memory mapping facilities described in this chapter can
be used to divide this physical memory up into segments and/or pages.

Starting with the Pentium Pro processor, the IA-32 architecture also supports an extension of the
physical address space to 2

36

 bytes (64 GBytes); with a maximum physical address of

FFFFFFFFFH. This extension is invoked in either of two ways:

•

Using the physical address extension (PAE) flag, located in bit 5 of control register CR4. 

•

Using the 36-bit page size extension (PSE-36) feature (introduced in the Pentium III
processors).

See Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism” and Section 3.9,
“36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” for more information about
36-bit physical addressing.