ARM R4 Manuale Utente

ARM DDI 0363E

4-21

ID013010

To access the Debug Feature Register 0 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 2 ; Read Debug Feature Register 0

The Auxiliary Feature Register 0 provides additional information about the features of the 
processor.

The Auxiliary Feature Register 0 is:
•

a read-only register

•

accessible in Privileged mode only.

In this processor, the Auxiliary Feature Register 0 reads as 

0x00000000

.

To access the Auxiliary Feature Register 0 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 3 ; Read Auxiliary Feature Register 0.

There are four Memory Model Feature Registers, MMFR0 to MMFR3. They are described in 
the following subsections:
•

•

•

•

The Memory Model Feature Register 0 provides information about the memory model, memory 
management, and cache support operations of the processor.

The Memory Model Feature Register 0 is:
•

a read-only register

•

accessible in Privileged mode only.

Figure 4-15 on page 4-22 shows the bit arrangement for Memory Model Feature Register 0.

[11:8]

Core debug model - 
memory mapped

Indicates the type of embedded processor debug model that the processor supports:

0x4

, ARMv7 based model - memory mapped.

[7:4]

Secure debug model

Indicates the type of secure debug model that the processor supports:

0x0

, no support.

[3:0]

Core debug model - 
coprocessor

Indicates the type of applications processor debug model that the processor supports:

0x0

, no support.