ARM R4 Manuale Utente

ARM DDI 0363E

xvii

ID013010

This is the Technical Reference Manual (TRM) for the Cortex-R4 and Cortex-R4F processors. 
In this book the generic term processor means both the Cortex-R4 and Cortex-R4F processors. 
Any differences between the two processors are described where necessary.

 The  Cortex-R4F  processor  is a Cortex-R4 processor that includes the optional Floating Point 
Unit (FPU) extension, see Product revision information on page 1-24 for more information.

In this book, references to the Cortex-R4 processor also apply to the Cortex-R4F processor, 
unless the context makes it clear that this is not the case.

The rnpn identifier indicates the revision status of the product described in this book, where:
rn 

Identifies the major revision of the product.

Identifies the minor revision or modification status of the product.

This book is written for system designers, system integrators, and programmers who are 
designing or programming a System-on-Chip (SoC) that uses the processor.

This book is organized into the following chapters:

Read this for an introduction to the processor and descriptions of the major 
functional blocks.

Read this for a description of the processor registers and programming 
information.

Read this for a description of clocking and resetting the processor, and the steps 
that the software must take to initialize the processor after reset.

Read this for a description of the system control coprocessor registers and 
programming information.

Read this for a description of the functions of the Prefetch Unit (PFU), including 
dynamic branch prediction and the return stack.

Read this for a description of the Performance Monitoring Unit (PMU) and the 
event bus.