ARM R4 Manuale Utente

ARM DDI 0363E

9-23

ID013010

This section describes how to enable or disable AXI slave accesses to the cache RAMs. When 
caches are accessible by the AXI slave interface, the caches are considered to be cache-off from 
the processor. After turning the interface on or off, an 

ISB

 instruction must flush the pipeline so 

that all subsequent instruction fetches return valid data.

The following code is an example of enabling AXI slave accesses to the cache RAMs:

MRC p15, 0, R1, c1, c0, 1

; Read Auxiliary Control Register

ORR R1, R1, #0x1 <<24
DSB
MCR p15, 0, R1, c1, c0, 1

; enabled AXI slave accesses to the cache RAMs

ISB
; Clean entire data cache. This routine will depend on the data cache size. It can be 
omitted if it is known that the data cache has no dirty data 
Fetch from uncached memory
Fetch from uncached memory
Fetch from uncached memory
Fetch from uncached memory

The following code is an example of disabling AXI slave accesses to the cache RAMs. No cache 
invalidation is performed because it is assumed that, after accessing the cache RAMs, the AXI 
slave interface restored the previously valid data to them.

MRC p15, 0, R1, c1, c0, 1

; Read Auxiliary Control Register

BIC R1, R1, #0x1 <<24
DSB
MCR p15, 0, R1, c1, c0, 1

; disabled AXI slave accesses to the cache RAMs

ISB
Fetch from cached memory
Fetch from cached memory
Fetch from cached memory
Fetch from cached memory