ARM R4 Manuale Utente
Introduction
ARM DDI 0363E
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1.3.1
Data Processing Unit
The DPU holds most of the program-visible state of the processor, such as general-purpose
registers, status registers and control registers. It decodes and executes instructions, operating
on data held in the registers in accordance with the ARM Architecture. Instructions are fed to
the DPU from the PFU through a buffer. The DPU performs instructions that require data to be
transferred to or from the memory system by interfacing to the LSU. See Chapter 2
Programmer’s Model for more information.
registers, status registers and control registers. It decodes and executes instructions, operating
on data held in the registers in accordance with the ARM Architecture. Instructions are fed to
the DPU from the PFU through a buffer. The DPU performs instructions that require data to be
transferred to or from the memory system by interfacing to the LSU. See Chapter 2
Programmer’s Model for more information.
Floating Point Unit
The Floating Point Unit (FPU) is an optional part of the DPU which includes the VFP register
file and status registers. It performs floating-point operations on the data held in the VFP register
file. See Chapter 12 FPU Programmer’s Model for more information.
file and status registers. It performs floating-point operations on the data held in the VFP register
file. See Chapter 12 FPU Programmer’s Model for more information.
1.3.2
Load/store unit
The LSU manages all load and store operations, interfacing with the DPU to the TCMs, caches,
and L2 memory interfaces.
and L2 memory interfaces.
1.3.3
Prefetch unit
The PFU obtains instructions from the instruction cache, the TCMs, or from external memory
and predicts the outcome of branches in the instruction stream. See Chapter 5 Prefetch Unit for
more information.
and predicts the outcome of branches in the instruction stream. See Chapter 5 Prefetch Unit for
more information.
Branch prediction
The branch predictor is a global type that uses history registers and a 256-entry pattern history
table.
table.
Return stack
The PFU includes a 4-entry return stack to accelerate returns from procedure calls. For each
procedure call, the return address is pushed onto a hardware stack. When a procedure return is
recognized, the address held in the return stack is popped, and the prefetch unit uses it as the
predicted return address.
procedure call, the return address is pushed onto a hardware stack. When a procedure return is
recognized, the address held in the return stack is popped, and the prefetch unit uses it as the
predicted return address.
1.3.4
L1 memory system
The processor L1 memory system includes the following features:
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separate instruction and data caches
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flexible TCM interfaces
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64-bit datapaths throughout the memory system
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MPU that supports configurable memory region sizes
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export of memory attributes for L2 memory system
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parity or ECC supported on local memories.
For more information of the blocks in the L1 memory system, see:
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