ARM R4 Manuale Utente
Debug
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
11-3
ID013010
Non-Confidential, Unrestricted Access
11.2
About the debug unit
The processor debug unit assists in debugging software running on the processor. You can use
the processor debug unit, in combination with a software debugger program, to debug:
•
the processor debug unit, in combination with a software debugger program, to debug:
•
application software
•
operating systems
•
ARM processor-based hardware systems.
The debug unit enables you to:
•
•
stop program execution
•
examine and alter processor state
•
examine and alter memory and peripheral state
•
restart the processor.
You can debug software running on the processor in the following ways:
•
•
Halting debug-mode debugging
•
Monitor debug-mode debugging
•
Trace debugging, see ETM interface on page 1-11.
The processor debug unit conforms to the ARMv7 debug architecture. For more information see
the ARM Architecture Reference Manual.
the ARM Architecture Reference Manual.
11.2.1
Halting debug-mode debugging
When the processor debug unit is in Halting debug-mode, the processor halts when a debug
event, such as a breakpoint, occurs. When the processor is halted, an external debugger can
examine and modify the processor state using the APB slave port. This debug mode is invasive
to program execution.
event, such as a breakpoint, occurs. When the processor is halted, an external debugger can
examine and modify the processor state using the APB slave port. This debug mode is invasive
to program execution.
11.2.2
Monitor debug-mode debugging
When the processor debug unit is in Monitor debug-mode, the processor takes a debug
exception instead of halting. A special piece of software, a monitor target, can then take control
to examine or alter the processor state. Monitor debug-mode is essential in real-time systems
where the processor cannot be halted to collect information. Examples of these systems are
engine controllers and servo mechanisms in hard drive controllers that cannot stop the code
without physically damaging the components.
exception instead of halting. A special piece of software, a monitor target, can then take control
to examine or alter the processor state. Monitor debug-mode is essential in real-time systems
where the processor cannot be halted to collect information. Examples of these systems are
engine controllers and servo mechanisms in hard drive controllers that cannot stop the code
without physically damaging the components.
When debugging in Monitor debug-mode, the processor stops execution of the current program
and starts execution of a monitor target. The state of the processor is preserved in the same
manner as all ARM exceptions. The monitor target communicates with the debugger to access
processor and coprocessor state, and to access memory contents and peripherals. Monitor
debug-mode requires a debug monitor program to interface between the debug hardware and the
software debugger.
and starts execution of a monitor target. The state of the processor is preserved in the same
manner as all ARM exceptions. The monitor target communicates with the debugger to access
processor and coprocessor state, and to access memory contents and peripherals. Monitor
debug-mode requires a debug monitor program to interface between the debug hardware and the
software debugger.
11.2.3
Programming the debug unit
The processor debug unit is programmed using the APB slave interface. See Table 11-3 on
page 11-6 for a complete list of memory-mapped debug registers accessible using the APB slave
interface. Some features of the debug unit that you can access using the memory-mapped
registers are:
page 11-6 for a complete list of memory-mapped debug registers accessible using the APB slave
interface. Some features of the debug unit that you can access using the memory-mapped
registers are:
•
instruction address comparators for triggering breakpoints, see Breakpoint Value
Registers on page 11-23 and Breakpoint Control Registers on page 11-23
Registers on page 11-23 and Breakpoint Control Registers on page 11-23